2.3.4. Distribution of global clocks to stacked
daughterboards
The V2F-2XV6 13MG daughterboard is designed to enable two
daughterboards for each motherboard site to have a common synchronous
clock. Figure 2.11 shows
the recommended clocking scheme to distribute a global clock from
the motherboard to two stacked daughterboards. You can use this
scheme in both motherboard sites to enable four daughterboards to
share a common synchronous clock.
Note
Figure 2.11 shows the recommended scheme to distribute
the global clocks to stacked V2F-2XV6 13MG daughterboards occupying
the motherboard sites. Figure 2.11 shows the clocking scheme for site 2,
and the same clocking scheme for site 1 is indicated by the partial
block on the left of Figure 2.11.
DDR FF are logic cells and BUFG are buffers provided
by Xilinx within the Virtex-6 FPGAs. This clocking scheme uses them
to propagate the clocks with identical delays. See the Virtex-6 FPGA
SelectIO Resources User Guide at the Xilinx web site for
more information.
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