2.2.3. High-speed buses to other daughterboard

The HDRXL header connects one Master, M, and one Slave, S, HSB, one full duplex bus lane, from FPGA 2 to the other daughterboard through dedicated headers on the motherboard. The most common use of this bus lane is to implement multiplexed AXI master and slave interfaces between the daughterboards.


Application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4, provides an example AXI design implementing external multiplexed AXI master and slave buses at the HDRXL header. See FPGA bus widths.

Copyright © 2010-2014 ARM. All rights reserved.ARM DUI 0556G