A.1.6. P-JTAG connector

The P-JTAG connector is provided on the daughterboard to enable connection of RealView ICE or a compatible third-party debugger. Figure A.4 shows the P-JTAG connector, J11, that is connected to FPGA 2.

Note

DBGRQ has a pull-down resistor to 0V. DBGACK has no pull-up or pull-down resistor. All other signal connections on the P-JTAG connector have pull-up resistors to 2V5.

Figure A.4. P-JTAG connector, J11

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Table A.4 lists the JTAG pin mapping for each JTAG signal. See the v2f_760.ucf constraints file, available in application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4, for FPGA mapping.

Table A.4. P-JTAG connector, J11, signal list

Pin Signal Pin Signal
1VIREF2VSUPPLYA
3nTRST4GND
5TDI6GND
7TMS8GND
9TCK10GND
11RTCK12GND
13TDO14GND
15nSRST16GND
17DBGRQ18GND
19DBGACK20GND

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