A.1.8. HSSTP connector

The daughterboard includes the interconnect to implement a High Speed Serial Trace Port (HSSTP), connected to FPGA 1 and FPGA 2. The interconnect supports six lanes of LVDS signaling. Figure A.6 shows the HSSTP connector, J7.

Note

Pins 2, 4, and 8 on the HSSTP connector have pull-up resistors to 2V5.

Figure A.6. HSSTP connector, J7

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table A.7 lists the HSSTP pin mapping. See the v2f_760.ucf constraints file for trace and debug to FPGA 2 mapping. See the v2f_550t.ucf constraints file for serial line to FPGA 1 mapping. Both constraints files are available in application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4.

Table A.7. HSSTP connector, J10, signal list

PinSignalPinSignal
1HSSTP_TX4_P2HSSTP_VTREF
3HSSTP_TX4_N4HSSTP_TCK
5GND6GND
7HSSTP_TX2_P8HSSTP_TMS
9HSSTP_TX2_N10nTRST
11GND12GND
13HSSTP_TX0_P14TDI
15HSSTP_TX0_N16TDO
17GND18GND
19HSSTP_CLK_P20nSRST
21HSSTP_CLK_N22HSSTP_DBGREQ
23GND24GND
25HSSTP_TX1_P26HSSTP_DBGACK
27HSSTP_TX1_N28RTCK
29GND30GND
31HSSTP_TX3_P32HSSTP_TRIGIN
33HSSTP_TX3_N34HSSTP_TRIGOUT
35GND36GND
37HSSTP_TX5_P38GND
39HSSTP_TX5_N40GND

Table A.8 shows the HSSTP TX FPGA 1-GTX connectivity.

Table A.8. HSSTP TX signal FPGA 1-GTX connectivity

HSSTP signalGTX location
HSSTP_TX0_PX0Y29
HSSTP_TX0_N
HSSTP_TX1_PX0Y28
HSSTP_TX1_N
HSSTP_TX2_PX0Y30
HSSTP_TX2_N
HSSTP_TX3_PX0Y27
HSSTP_TX3_N
HSSTP_TX4_PX0Y31
HSSTP_TX4_N
HSSTP_TX5_PX0Y26
HSSTP_TX5_N

Copyright © 2010-2014 ARM. All rights reserved.ARM DUI 0556G
Non-ConfidentialID052914