2.2.4. High-speed buses between the FPGAs, FPGA LINK

292 single-ended IO signals are available between FPGA 1 and FPGA 2. You can use these as discrete IO, or you can configure them as up to 146 LVDS pairs. See Figure 2.3. You can implement a HSB, for example AXI, between the FPGAs. You can implement a Master, M, interface and a Slave, S, interface on each FPGA to form one full duplex bus lane. See Figure 2.12 and Figure 2.13.

Note

Application note AN233 implements the HSB link between the FPGAs using the FPGA LINK bus. See FPGA bus widths.

Copyright © 2010-2014 ARM. All rights reserved.ARM DUI 0556G
Non-ConfidentialID052914