A.1.7. SATA connectors

Two SATA connectors on the daughterboard are connected to FPGA 1. Connectivity for two SATA Host, H, and two SATA Device, D, interfaces is provided. Figure A.5 shows the SATA connector.

Figure A.5. SATA connector, J8 and J18

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Table A.5 lists the SATA Host pin mapping for each SATA signal.

Note

The GTX location for the SATA Host signals is X0Y24. See the v2f_550t.ucf constraints file, available in application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4, for FPGA mapping.

Table A.5. SATA Host, J8, signal list

PinSignal
S1GND
S2SATAH_A_P
S3SATAH_A_N
S4GND
S5SATAH_B_N
S6SATAH_B_P
S7GND

Table A.6 lists the SATA Device pin mapping for each SATA signal.

Note

The GTX location for the SATA Device signals is X0Y25. See the v2f_550t.ucf constraints file, available in application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4, for FPGA mapping.

Table A.6. SATA Device, J18, signal list

PinSignal
S1GND
S2SATAD_A_P
S3SATAD_A_N
S4GND
S5SATAD_B_N
S6SATAD_B_P
S7GND

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