2.2.11. ZBT memory interface

This is implemented in FPGA 2. The ZBT memory interface controls two independent 8MB ZBT SRAM parts. Figure 2.5 shows the generic FPGA to ZBT SRAM interconnect.

Application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4, contains an example AXI to ZBT controller, netlist only.

Figure 2.5. Dual ZBT SRAM interface

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