2.2.10. PCI-Express Bus (PCIe)

The V2F-2XV6 can implement a root complex to connect, through the motherboard PCIe switch, to the PCI Express Gen1 Card slots on the motherboard. The daughterboard supports a maximum of eight lanes downwards to header HDRYL.

The daughterboard can implement an endpoint which supports a maximum of eight lanes upwards to header HDRYU.

Figure 2.4 shows the PCI-Express signals to the headers. Table 2.1 shows the connectivity between the Gigabit Transceiver (GTX) locations in the FPGA and the PCI Express lanes.

Note

Xilinx supplies the PCIe endpoint and the PCIe root port in the Virtex-6 FPGA as hardblocks. You can implement them using Xilinx tool flow. You can implement a PCIe root complex using a third party IP softblock.

Note

The V2M-P1 motherboard can support a root complex either on the daughterboard in Site 1 or the daughterboard in Site 2, but not both. You select which site contains the root complex by editing the config.txt. By default, the daughterboard in Site 1 is the root complex.

The V2M-P1 motherboard tile sites do not support endpoints in the daughterboards connected to the switch.

Figure 2.4. PCI express bus connections

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Caution

You can configure the sideband signals PCIe_nWAKE, PCIe_PERST, and PCIe_nRST as either inputs or outputs. If you configure them as outputs, they must be set to be open-collector.

Note

  • When the daughterboard is fitted to the motherboard, HDRYU is on the upper side of the board facing away from the motherboard, and HDRYL is on the lower side of the board facing towards the motherboard.

  • Clocks PCIe_UP_REFCLK and PCIe_UP_LOCAL_REFCLK are synchronous.

Table 2.1 shows, for the upper header, the connectivity between the Gigabit Transceiver (GTX) locations in FPGA 1 and the PCI-Express lanes.

Table 2.1. Upper header PCI-Express Lanes. FPGA 1-GTX connectivity

PCIe laneGTX location
Lane 0X0Y15
Lane 1X0Y14
Lane 2X0Y13
Lane 3X0Y12
Lane 4X0Y11
Lane 5X0Y10
Lane 6X0Y9
Lane 7X0Y8

Table 2.2 shows, for the lower header, the connectivity between the GTX locations in FPGA 1 and the PCI-Express lanes.

Table 2.2. Lower header PCI-Express Lanes. FPGA 1-GTX connectivity

PCIe laneGTX location
Lane 0X0Y23
Lane 1X0Y22
Lane 2X0Y21
Lane 3X0Y20
Lane 4X0Y19
Lane 5X0Y18
Lane 6X0Y17
Lane 7X0Y16

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