3.4.2. DCC_LOCK Register

The DCC_LOCK Register characteristics are:

Purpose

PLL lock status bits from the FPGA.

Usage constraints

There are no usage constraints.

Configurations

Available in all LogicTile Express 13MG configurations.

Attributes

Figure 3.2 shows the bit assignments.

Figure 3.2. DCC_LOCK Register bit assignments

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Table 3.3 shows the bit assignments.

Table 3.3. DCC_LOCK Register bit assignments

BitsNameFunction
[31:24]LOCK_MASK[7:0]These bits indicate whether the individual lock bits are masked.
[23:16]LOCK_STATUS[7:0]

These bits indicate the individual lock status:

b0

Unlocked.

b1

Locked.

[15:1] -Reserved.
[0]LOCKED

This bit indicates whether all unmasked lock bits are locked:

b0

Unlocked.

b1

Locked.


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