3.2. Register summary

Table 3.1 shows the registers in offset order from the base memory address.

Table 3.1. Register summary

Offset

Name

Type

Reset

Width

Description

0x000-0x0FCDCC_CFGxRW0xXXXXXXXX[a]32DCC_CFGx registers
0x100DCC_LOCKRO0xFFXX000X[b]32DCC_LOCK Register
0x104DCC_LEDRO0x0000000F32DCC_LED Register
0x108DCC_SWRO0x0000000032DCC_SW Register
0xFF8DCC_AIDRO0xXXXXXXXX[a]32DCC_AID Register
0xFFCDCC_IDRO0xXXXXXXXX[a]32DCC_ID Register

[a] Where X = unknown at reset.

[b] Last X = b000X, either b0000 or b0001.


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