2.5.2. Clock domains

Figure 2.12 shows the FPGA 1 clock domains.

Figure 2.12. FPGA 1 clock domains

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Clock loops DDR_LOOP, XU_LOOP, and ZBT_LOOP are available to enable you to use phase-shifted clocks internally in your design while transmitting the non phase-shifted clock externally. See Figure 2.12 and Figure 2.13. Application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4 contains an example use of phase-shifted clocks.

Note

Figure 2.12 shows the clocks available to implement the functions shown as blocks inside the FPGAs. See the an233_760.ucf and an233_550t.ucf constraints files supplied in application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4. This application note implements the functions shown as solid blocks. It does not supply the functions shown as dashed blocks.

Figure 2.13 shows the FPGA 2 clock domains.

Figure 2.13. FPGA 2 clock domains

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Note

Figure 2.13 shows the clocks available to implement the functions shown as blocks inside the FPGAs. See the an233_760.ucf and an233_550t.ucf constraints files supplied in application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4. This application note implements the functions shown as solid blocks. It does not supply the functions shown as dashed blocks.

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