2.2.5. Buses for upward expansion

The daughterboard can support bus links from FPGA 1 through upper header HDRYU, and from FPGA 2 through upper header HDRXU to another LogicTile Express 13MG daughterboard or user IO expansion board.

340 single-ended IO signals are available between FPGA 2 and upper header HDRXU. You can configure up to 320 of these signals as 160 LVDS pairs. You can only use the other 20 signals as single-ended IO. You can use these signals to implement a HSB bus, for example AXI, to the upper LogicTile 13MG daughterboard or user IO expansion board.

182 single-ended signals are available between FPGA 1 and upper header HDRYU. You can use these signals to implement other buses, for example, SMB, MMB, or SB, to the upper LogicTile 13MG daughterboard or user IO expansion board.

Note

  • Application note AN233 does not implement these links but you can implement them yourself using the 160 LVDS pairs and 20 IO signals available between FPGA 1 and header HDRXU, and the 182 single-ended signals available between FPGA 1 and header HDRYU. See FPGA bus widths.

  • If LogicTile daughterboards are stacked, an external ATX power supply is required.

  • LogicTile Express 3MG, V2F-1XV5, boards are not stackable on top of LogicTile Express 13MG, V2F-2XV6, boards because the two boards use different Daughterboard Configuration Controller addressing schemes.

  • ARM recommends a maximum stack of two LogicTile Express 13MG boards, and two boards per motherboard site, to enable the use of a common synchronous clock. See Distribution of global clocks to stacked daughterboards.

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