2.5.1. Overview of clocks

The majority of the clocks that the daughterboard uses are generated locally by two on-board clock generators, or within the FPGAs. Each clock generator is associated with one of the FPGAs and contains three oscillators that drive three clocks to its associated FPGA. Figure 2.12 and Figure 2.13 show the clock domains of the daughterboard.

The MCC transfers clock settings to Daughterboard Configuration Controller 1 during power-up sequencing using values that the daughterboard configuration files define. Daughterboard Configuration Controller 1 then configures the programmable clock generators.

Table 2.4 shows information on the daughterboard clocks.

Table 2.4. LogicTile Express 13MG daughterboard clocks

Daughterboard clocksSourceFrequency rangeComment
OSC[2:0]CLK GEN 1

2MHz-230MHz

1% resolution

Variables OSC0, OSC1 and OSC2 in file f550r0p1.txt configure these daughterboard clocks.

OSC[5:3]CLK GEN 2

2MHz-230MHz

1% resolution

Variables OSC3, OSC4 and OSC5 in file f550r0p1.txt configure these daughterboard clocks.

SER_CLKSER CLK GENFixed 150MHzThis is for use if you implement an interface over the SATA connectors.

PCIE_UP_REFCLK

PCIE_REFCLK

LOCAL PCIE REFCLK

Fixed 100MHz-

HSSTP_CLK

External clock-

The LogicTile Express 13MG daughterboard does not generate this clock.

See the Xilinx website for information on clock frequencies that the XC6VLX550T FPGA can accept.


See the ARM® Versatile™ Express Configuration Technical Reference Manual for information on how to adjust the clock values. Additionally, you can read and write to the daughterboard while the system is running, using the motherboard SYS_CFG register interface.

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