2.5.3. Global clocks

The global clocks, GCLK*, on the daughterboard are delay-matched so that they remain synchronous when FPGA 1, FPGA 2, and devices on other boards receive them. See Figure 2.14. The track lengths of clocks MB_GCLK1 and MB_GCLK2 are delay-matched to length L. GCLK_F2F2 and GLCK_F2F1 are delay-matched to length 2L. This enables two LogicTile Express 13MG, V2F-2XV6, daughterboards placed in site 1 and site 2 to receive the synchronous motherboard global clocks. The motherboard drives these clocks to both sites and its clock track lengths are also delay-matched to length L.

Clocks GCLK_UP0, GCLK_UP1, and GCLK_UP2 are delay-matched to length L. This enables another daughterboard or expansion board that also has matched clock lengths of L, connected to upper connector HDRYU, to receive the synchronous clocks at the same time as FPGA 1 and FPGA 2 on the LogicTile Express V2F-2XV6 daughterboard.

Figure 2.14. Delay-matched clocks

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Note

The matched clock length L is 7192 ± 10 mil.

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