2.8. Minimum design settings for daughterboard operation

The minimum RTL in both LogicTile Express FPGAs to operate correctly involves:

  1. Set the SMB_CLKO signal to the inactive LOW state as follows:

    Tie SMB_CLKO to b0.

    Note

    This stops data being clocked to the IOFPGA on the motherboard.

  2. Set the SMB chip select to the inactive HIGH state as follows:

    Tie the chip selects SMB_nCS to b11111111.

    Note

    This stops static memory access to the motherboard.

  3. Set the CFGATAOUT signal to the inactive LOW state as follows:

    Tie NAND_D[5] to b0, as the note in Serial Configuration Controller (SCC) describes.

    Note

    This informs the Daughterboard Configuration Controller that the V2F-2XV6 daughterboard does not implement any of its features.

  4. Set the nRSTREQ signal to the inactive HIGH state as follows:

    Tie NAND_D[7] to b1.

    Note

    This prevents nRSTREQ from generating a reset. nRSTREQ is usually a system-wide master soft reset signal that is both generated and observed by the JTAG debug box.

Note

ARM recommends that all unused pins be tied to their inactive states.

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