ARM® LogicTile Express 13MG Technical Reference Manual

V2F-2XV6


Table of Contents

Preface
About this book
Intended audience
Using this book
Glossary
Typographical conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. Precautions
1.1.1. Ensuring safety
1.1.2. Preventing damage
1.2. About the LogicTile Express 13MG daughterboard
2. Hardware Description
2.1. Overview of the daughterboard hardware
2.2. System interconnect
2.2.1. Overview of system interconnect
2.2.2. FPGA bus widths
2.2.3. High-speed buses to other daughterboard
2.2.4. High-speed buses between the FPGAs, FPGA LINK
2.2.5. Buses for upward expansion
2.2.6. Static Memory Bus (SMB)
2.2.7. MultiMedia Bus (MMB)
2.2.8. System Bus (SB)
2.2.9. Configuration Bus (CB)
2.2.10. PCI-Express Bus (PCIe)
2.2.11. ZBT memory interface
2.2.12. DDR2 memory interface, SO-DIMM
2.2.13. FPGA configuration Flash memory interface
2.2.14. SATA connectors
2.3. FPGA configuration and initialization
2.3.1. Configuration hardware
2.3.2. FPGA image programming and daughterboard configuration
2.3.3. Resets
2.4. Daughterboard Configuration Controller - FPGA SCC interface
2.4.1. Overview of Daughterboard Configuration Controller-FPGA SCC interface
2.4.2. Serial Configuration Controller (SCC)
2.5. Clocks
2.5.1. Overview of clocks
2.5.2. Clock domains
2.5.3. Global clocks
2.5.4. Distribution of global clocks to stacked daughterboards
2.6. Voltage, temperature, oscillator, and SCC register monitoring
2.6.1. Overview of voltage, temperature, oscillator and SCC monitoring.
2.6.2. Information transmitted by Daughterboard Configuration Controller 1 to the motherboard
2.6.3. Information transmitted by Daughterboard Configuration Controller 2 to the motherboard
2.6.4. Daughterboard shutdown because of excessive temperature
2.7. FPGA debug and trace
2.7.1. Overview of debug and trace
2.7.2. F-JTAG
2.7.3. P-JTAG
2.7.4. Trace
2.7.5. HSSTP
2.8. Minimum design settings for daughterboard operation
3. Programmers Model
3.1. About this programmers model
3.2. Register summary
3.3. Memory map
3.4. SCC register descriptions
3.4.1. DCC_CFGx registers
3.4.2. DCC_LOCK Register
3.4.3. DCC_LED Register
3.4.4. DCC_SW Register
3.4.5. DCC_AID Register
3.4.6. DCC_ID Register
A. Signal Descriptions
A.1. Daughterboard connectors
A.1.1. Header connectors on lower side of board
A.1.2. Header connectors on upper side of board
A.1.3. SO-DIMM connector
A.1.4. Trace connectors
A.1.5. F-JTAG (ILA) connector
A.1.6. P-JTAG connector
A.1.7. SATA connectors
A.1.8. HSSTP connector
B. Specifications
B.1. Electrical specification
B.1.1. FPGA current requirements
C. Revisions

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The system should be powered down when not in use.

The LogicTile Express 13MG generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • Ensure attached cables do not lie across the card.

  • Reorient the receiving antenna.

  • Increase the distance between the equipment and the receiver.

  • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

  • Consult the dealer or an experienced radio/TV technician for help.

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision A21 September 2010First release
Revision B28 March 2011Second Release
Revision C22 June 2012Third Release
Revision D12 October 2012Fourth Release
Revision E31 March 2013Fifth Release
Revision F29 October 2013Sixth Release
Revision G28 May 2014Seventh Release
Copyright © 2010-2014 ARM. All rights reserved.ARM DUI 0556G
Non-ConfidentialID052914