3.3.5.  Restrictions on the processor models

Detailed information concerning what features are not fully implemented in the processor models included with the VE RTSMs can be found in separate documentation. See the Fast Models Reference Manual. The following general restrictions apply to the Real-Time System Model implementations of ARM processors:

RTSM_VE_Cortex-A9 coretile

The following additional restrictions apply to the Real-Time System Model implementation of a Cortex-A9 MPCore processor:

  • The Cortex-A9MPCore processor contains some memory-mapped peripherals. These are modeled by the RTSM.

  • Two 4GB address spaces are seen by the model core, one as seen from secure mode and one as seen from normal mode. The address spaces contain zero-wait state memory and peripherals, but a lot of the space is unmapped.

  • The RR bit in the SCTLR is ignored.

  • The Power Control Register in the system control coprocessor is implemented but writing to it does not change the behavior of the model.

  • The SCU is only partially modeled:

    • The SCU enable bit is ignored. The SCU is always enabled.

    • The SCU ignores the invalidate all register.

    • Coherency operations are represented by a memory write followed by a read to refill from memory, rather than using cache-to-cache transfers.

    • There is no address filtering within the SCU. The enable bit for this feature is ignored.

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