3.2.3. RTSM_VE_Cortex-A15MPx1, RTSM_VE_Cortex-A15MPx2 and RTSM_VE_Cortex-A15MPx4 coretile parameters

Table 3.16 lists the Cortex-A15 multiprocessor coretile parameters that you can change when you start the RTSM_VE_Cortex-A15MPx1, RTSM_VE_Cortex-A15MPx2 or RTSM_VE_Cortex-A15MPx4 models. All listed parameters are instantiation-time parameters. This coretile RTSM is based on r2p0 of the Cortex-A15 processor.

The syntax to use in a configuration file is:


Table 3.16. RTSM_VE_Cortex-A15MPxn coretile parameters

ParameterDescriptionTypeAllowed ValueDefault Value
CFGSDISABLEDisable some accesses to DIC registers.booleantrue or falsefalse
CLUSTER_ID CPU cluster ID value.integer0-150
IMINLNInstruction cache minimum line size: false=32 bytes, true=64 bytesboolean true or falsetrue
PERIPHBASEBase address of peripheral memory space.integer-0x13080000[a]
dic-spi_countNumber of shared peripheral interrupts implemented.integer0-224, in increments of 3264
internal_vgicConfigures whether the model of the core contains a Virtual Generic Interrupt Controller (VGIC).booleantrue or falsetrue
l1_dcache-state_modelledSet whether L1 D-cache has stateful implementationbooleantrue or falsefalse
l1_icache-state_modelledSet whether L1 I-cache has stateful implementationbooleantrue or falsefalse
l2_cache-sizeSet L2 cache size in bytesinteger0x080000, 0x100000, 0x200000, 0x400000.0x400000
l2_cache-state_modelledSet whether L2 cache has stateful implementationbooleantrue or falsefalse
l2-data-sliceL2 data RAM slice.integer0, 1 or 20
l2-tag-sliceL2 tag RAM slice.integer0 or 10

[a] If you are using the ARMCortexA15xnCT component on a VE model platform, this parameter is set automatically to 0x1F000000 and is not visible in the parameter list.

The RTSM_VE_Cortex-A15MPx1 has the PERIPHBASE parameter set to 0x1F000000, which is the base address of peripheral memory space on VE hardware.

Table 3.17 provides a description of the configuration parameters for each Cortex-A15MP core. These parameters are set individually for each Cortex-A15 core you have in your system. Each core has its own timer and watchdog.

The syntax to use in a configuration file is:


where n is the CPU number, from 0 to 3 inclusive.

Table 3.17. RTSM_VE_Cortex-A15MPxn coretile parameters - individual cores

ParameterDescriptionTypeAllowed ValueDefault Value
CFGENDInitialize to BE8 endianness.booleantrue or falsefalse
CFGNMFIEnable nonmaskable FIQ interrupts on startup.booleantrue or falsefalse
CP15SDISABLEInitialize to disable access to some CP15 registers.booleantrue or falsefalse
DBGROMADDRThis value is used to initialize the CP15 DBGDRAR register. Bits[39:12] of this register specify the ROM table physical address.integer0x120000030x12000003
DBGROMADDRVIf true, this sets bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid.booleantrue or falsetrue
DBGSELFADDRThis value is used to initialize the CP15 DBGDSAR register. Bits[39:17] of this register specify the ROM table physical address.integer0x000100030x00010003
DBGSELFADDRVIf true, this sets bits[1:0] of the CP15 DBGDSAR to indicate that the address is valid.booleantrue or falsetrue
POWERCTLIDefault power control state for CPU.integer0-30
SMPnAMPSet whether the processor is part of a coherent domain.booleantrue or falsefalse
TEINITThumb exception enable. The default has exceptions including reset handled in ARM state.booleantrue or falsefalse
VINITHIInitialize with high vectors enabled.booleantrue or falsefalse
ase-present[a]Set whether processor model has been built with NEON™ support.booleantrue or falsetrue
min_sync_levelControls the minimum syncLevel by the CADI parameter interface.integer0-30
semihosting-cmd_lineCommand line available to semihosting SVC calls.stringno limit except memory[empty string]
semihosting-debug[b]Enable debug output of semihosting SVC calls.booleantrue or falsefalse
semihosting-enableEnable semihosting SVC traps.booleantrue or falsetrue
semihosting-ARM_SVCARM SVC number for semihosting.integer0x000000 - 0xFFFFFF0x123456
semihosting-Thumb_SVCThumb SVC number for semihosting.integer0x00 - 0xFF0xAB
semihosting-heap_baseVirtual address of heap base.integer0x00000000 - 0xFFFFFFFF0x0
semihosting-heap_limitVirtual address of top of heap.integer0x00000000 - 0xFFFFFFFF0x0F000000
semihosting-stack_baseVirtual address of base of descending stack.integer0x00000000 - 0xFFFFFFFF0x10000000
semihosting-stack_limitVirtual address of stack limit.integer0x00000000 - 0xFFFFFFFF0x0F000000
vfp-enable_at_reset[c]Enable coprocessor access and VFP at reset.booleantrue or falsefalse
vfp-present[a]Set whether processor model has been built with VFP support.booleantrue or falsetrue

[a] The ase-present and vfp-present parameters configure the synthesis options for the Cortex-A15 model. The options are:

vfp present and ase present

NEON and VFPv3-D32 supported.

vfp present and ase not present

VFPv3-D16 supported.

vfp not present and ase present

Illegal. Forces vfp-present to true so model has NEON and VFPv3-D32 support.

vfp not present and ase not present

Model has neither NEON nor VFPv3-D32 support.

[b] Currently ignored.

[c] This is a model specific behavior with no hardware equivalent.

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