Using the MPS Visualisation window

When a MPS RTSM starts, the RTSM CLCD window opens, representing the contents of the simulated color LCD frame buffer. It automatically resizes to match the horizontal and vertical resolution set in the CLCD peripheral registers.

The following figure shows the MPS RTSM CLCD in its default state, immediately after being started.

Figure 6. Visualisation window at startup

Visualisation window at startup

The top section of the CLCD window displays the following status information:

Character LCD

The large box shows the state of the character LCD.

CPU

Eight colored circles indicate the state of the CPU LEDs.

DUT

Eight colored circles indicate the state of the DUT LEDs.

Fan

Two colored circles indicate the state of the fan LEDs.

Power

Four colored circles indicate the state of the power LEDs.

FPGA Config

Three colored circles indicate the state of the FPGA configuration LEDs.

SD

The box with the letters SD indicates the state of the SD memory. Click the box to enable or disable the device.

DIP CPU

Eight white boxes show the state of the CPU switches.

DIP DUT

Four white boxes show the state of the DUT switches.

Note

ARM recommends that you configure the Boot DIP switches using the boot_switch model parameter instead of using the CLCD interface.

Changing Boot DIP switch positions while the model is running can result in unpredictable behavior.

Total Instr

A counter showing the total number of instructions executed.

The system models provide a programmer’s view of the system, so the total instructions are displayed rather than total core cycles. Timing might differ substantially from the hardware because:

  • the bus fabric is simplified

  • memory latencies are minimized

  • cycle approximate core and peripheral models are used.

In general bus transaction timing is consistent with the hardware, but timing of operations within the model is not accurate.

Total Time

A counter showing the total elapsed time, in seconds.

This is wall clock time, not simulated time.

Rate Limit

A feature that disables or enables fast simulation.

Because the system model is highly optimized, your code might run faster than it would on real hardware. This might cause timing issues.

If Rate Limit is enabled, the default simulation time is restricted so that it more closely matches real time.

Click on the square button to disable or enable Rate Limit. The text changes from ON to OFF and the colored box becomes darker when Rate Limit is disabled. The figure below shows the CLCD with Rate Limit enabled.

Note

You can control whether Rate Limit is enabled by using the rate_limit-enable parameter, one of the visualisation parameters for the MPS Visualisation component, when instantiating the model.

CLCD display

The large area at the bottom of the window displays the contents of the CLCD buffer. The following figure shows this:

Figure 7. Visualisation window with CLCD buffer displayed

Visualisation window with CLCD buffer displayed

If the CLCD component is not used in the simulation, the display area is black.

You can hide the host mouse pointer by pressing the Left Ctrl+Left Alt keys. Press the keys again to redisplay the host mouse pointer. Only the Left Ctrl key is operational. The Right Ctrl key on the right of the keyboard does not have the same effect.

If you prefer to use a different key, use the trap_key configuration option, one of the visualisation parameters for the MPS Visualisation component.

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