VE model memory map

The following table shows the global memory map for the platform model. This map is based on the Versatile Express RS1 memory map with the RS2 extensions.

Table 2. Memory map

PeripheralModeledAddress rangeSize
NOR FLASH0 (CS0)Yes0x00_00000000-0x00_03FFFFFF64MB
Reserved-0x00_04000000-0x00_07FFFFFF64MB
NOR FLASH0 alias (CS0)Yes0x00_08000000-0x00_0BFFFFFF64MB
NOR FLASH1 (CS4)Yes0x00_0C000000-0x00_0FFFFFFF64MB
Unused (CS5)-0x00_10000000-0x00_13FFFFFF-
PSRAM (CS1) - unusedNo0x00_14000000-0x00_17FFFFFF-
Peripherals (CS2). See Table 4.Yes0x00_18000000-0x00_1BFFFFFF64MB
Peripherals (CS3). See Table 5.Yes0x00_1C000000-0x00_1FFFFFFF64MB
CoreSight and peripheralsNo0x00_20000000-0x00_2CFFFFFF[a]-
Graphics spaceNo0x00_2D000000-0x00_2D00FFFF-
System SRAMYes0x00_2E000000-0x00_2EFFFFFF64KB
Ext AXINo0x00_2F000000-0x00_7FFFFFFF-
4GB DRAM (in 32-bit address space)[b]Yes0x00_80000000-0x00_FFFFFFFF2GB
Unused-0x01_00000000-0x07_FFFFFFFF-
4GB DRAM (in 36-bit address space)[b]Yes0x08_00000000-0x08_FFFFFFFF4GB
Unused-0x09_00000000-0x7F_FFFFFFFF-
4GB DRAM (in 40-bit address space)[b]Yes0x80_00000000-0xFF_FFFFFFFF4GB

[a] The private peripheral region address 0x2c000000 is mapped in this region. The parameter PERIPHBASE can be used to map the peripherals to a different address.

[b] The model contains only 4GB of DRAM. The DRAM memory address space is aliased across the three different regions and where the mapped address space is greater than 4GB.


The model has a secure_memory option. When you enable this option, the memory map is changed for a number of peripherals as shown in the following table:

Table 3. CS2 peripheral memory map for secure_memory option

PeripheralAddress rangeFunctionality with secure_memory enabled
NOR FLASH0 (CS0)0x00_00000000-0x00_0001FFFFSecure RO, aborts on non-secure accesses.
Reserved0x00_04000000-0x00_0401FFFFSecure SRAM, aborts on non-secure accesses.
NOR FLASH0 alias (CS0)0x00_08000000-0x00_7DFFFFFFNormal memory map, aborts on secure accesses.
Ext AXI0x00_7e000000-0x00_7FFFFFFFSecure DRAM, aborts on non-secure accesses.
4GB DRAM (in 32-bit address space)0x00_80000000-0xFF_FFFFFFFFNormal memory mpa, aborts on secure accesses.

The following table shows details of the memory map for peripherals in the CS2 region:

Table 4. CS2 peripheral memory map

PeripheralModeledAddress rangeSizeGIC Int[a]
VRAM - aliasedYes0x00_18000000-0x00_19FFFFFF32MB-
Ethernet (SMSC 91C111)Yes0x00_1A000000-0x00_1AFFFFFF16MB47
USB - unusedNo0x00_1B000000-0x00_1BFFFFFF16MB-

[a] The Interrupt signal column lists the values to use to program your interrupt controller. The values shown are after mapping the SPI number by adding 32. The interrupt numbers from the peripherals are modified by adding 32 to form the interrupt number seen by the GIC. GIC interrupts 0-31 are for internal use.


The following table shows details of the memory map for peripherals in the CS3 region:

Table 5. CS3 peripheral memory map

PeripheralModeledAddress rangeSizeGIC Int[a]
Local DAP ROMNo0x00_1C000000-0x00_1C00FFFF64KB-
VE System RegistersYes0x00_1C010000-0x00_1C01FFFF64KB-
System Controller (SP810)Yes0x00_1C020000-0x00_1C02FFFF64KB-
TwoWire serial interface (PCIe)No0x00_1C030000-0x00_1C03FFFF64KB-
AACI (PL041)Yes0x00_1C040000-0x00_1C04FFFF64KB43
MCI (PL180)Yes0x00_1C050000-0x00_1C05FFFF64KB41, 42
KMI - keyboard (PL050)Yes0x00_1C060000-0x00_1C06FFFF64KB44
KMI - mouse (PL050)Yes0x00_1C070000-0x00_1C07FFFF64KB45
Reserved-0x00_1C080000-0x00_1C08FFFF64KB-
UART0 (PL011)Yes0x00_1C090000-0x00_1C09FFFF64KB37
UART1 (PL011)Yes0x00_1C0A0000-0x00_1C0AFFFF64KB38
UART2 (PL011)Yes0x00_1C0B0000-0x00_1C0BFFFF64KB39
UART3 (PL011)Yes0x00_1C0C0000- 0x00_1C0CFFFF64KB40
VFS2Yes0x00_1C0D0000-0x00_1C0DFFFF64KB73
Reserved-0x00_1C0E0000-0x00_1C0EFFFF64KB-
Watchdog (SP805)Yes0x00_1C0F0000-0x00_1C0FFFFF64KB32
Reserved-0x00_1C100000-0x00_1C10FFFF64KB-
Timer-0 (SP804)Yes0x00_1C110000-0x00_1C11FFFF64KB34
Timer-1 (SP804)Yes0x00_1C120000-0x00_1C12FFFF64KB35
Reserved-0x00_1C130000-0x00_1C15FFFF192KB-
TwoWire serial interface (DVI) - unusedNo0x00_1C160000-0x00_1C16FFFF64KB-
Real-time Clock (PL031)Yes0x00_1C170000-0x00_1C17FFFF64KB36
Reserved-0x00_1C180000-0x00_1C19FFFF128KB-
CF Card - unusedNo0x00_1C1A0000-0x00_1C1AFFFF64KB 
Reserved-0x00_1C1B0000-0x00_1C1EFFFF256KB-
Color LCD Controller (PL111)Yes0x00_1C1F0000-0x00_1C1FFFFF64KB46
Reserved-0x00_1C200000-0x00_1FFFFFFF62KB-

[a] The Interrupt signal column lists the values to use to program your interrupt controller. The values shown are after mapping the SPI number by adding 32. The interrupt numbers from the peripherals are modified by adding 32 to form the interrupt number seen by the GIC. GIC interrupts 0-31 are for internal use.


Note

The VE RTSM implementation of memory does not require programming the memory controller with the correct values.

This means you must ensure that the memory controller is set up properly if you run an application on actual hardware. If this is not done, applications that run on a RTSM might fail on actual hardware.

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