MPS model memory map

This section describes the MPS memory map. For standard ARM peripherals, see the TRM for that device.

Table 33. Overview of MPS memory map

DescriptionModelledAddress range
4MB Remap region for SRAM0 overlay of FlashYes0x00000000-0x003FFFFF
Non remapped Flash memoryYes0x00400000-0x03FFFFFF
SRAM for code and data storage (remap RAM)Yes0x10000000-0x103FFFFF
SRAM for code and data storageYes0x10400000-0x107FFFFF
FLASH aliased for programmingYes0x18000000-0x1BFFFFFF
CPU System RegistersYes0x1F000000-0x1F000FFF
Reserved for SMC configuration registersN/A0x1F001000-0x1F002FFF
I2C for DVIYes0x1F003000-0x1F003FFF
PL022 SPI for Touch ScreenYes0x1F004000-0x1F004FFF
PL011 UARTYes0x1F005000-0x1F005FFF
ReservedN/A0x1F006000-0x1FFFFFFF
SP805 Watch DogYes0x40000000-0x4000FFFF
PL031 RTCYes0x40001000-0x40001FFF
SP804 Timer (0)Yes0x40002000-0x40002FFF
SP804 Timer (1)Yes0x40003000-0x40003FFF
DUT Sys RegsYes0x40004000-0x40004FFF
PL181 SD/MMC controllerYes0x40005000-0x40005FFF
ReservedN/A0x40006000-0x40006FFF
PL011 UART (1)Yes0x40007000-0x40007FFF
PL011 UART (2)Yes0x40008000-0x40008FFF
PL011 UART (3)Yes0x40009000-0x40009FFF
PL041 AC97 controllerYes0x4000A000-0x4000AFFF
DS702 I2C (ADCDAC)Partial[a]0x4000B000-0x4000BFFF
DUT Character LCDYes0x4000C000-0x4000CFFF
ReservedN/A0x4000D000-0x4000EFFF
ReservedN/A0x4FFA0000-0x4FFAFFFF
FlexrayPartial[a]0x4FFB0000-0x4FFBFFFF
CANPartial[a]0x4FFC0000-0x4FFCFFFF
LINPartial[a]0x4FFD0000-0x4FFDFFFF
EthernetPartial[a]0x4FFE0000-0x4FFEFFFF
VideoYes0x4FFF0000-0x4FFFFFFF
External AHB interface to DUT FPGAYes0x50000000-0x5FFFFFFF
DMCYes0x60000000-0x9FFFFFFF
SMCYes0xA0000000-0xAFFFFFFF
Private Peripheral BusYes0xE0000000-0xE00FFFFF
System bus interface to DUT FPGAYes0xE0100000-0xFFFFFFFF

[a] This model is represented by a register bank and has no functionality beyond this.


Note

A Bus Error is generated for accesses to memory areas not shown in this table.

Any memory device that does not occupy the total region is aliased within that region.

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