RTSM_VE_Cortex-R5_MPx1 and RTSM_VE_Cortex-R5_MPx2 coretile parameters

The table below lists the configuration parameters for the following models:

These parameters are set once, irrespective of the number of Cortex-R5 processors in your system. If you have multiple Cortex-R5 processors, then each processor has its own parameters.

Table 21. RTSM_VE_CortexR5_MPxn coretile parameters

Parameter

Description

Type

Allowed Value

Default Value

GROUP_ID

Value read in GROUP ID register field, bits[15:8] of the MPIDR.

Integer

0-15

0

INST_ENDIAN

Controls whether the model supports the instruction endianness bit. You can find more information in the ARM Architecture Reference Manuals. See the reference information at the end of this topic.

Boolean

true/false

true

LOCK_STEP

Affects dual-processor configurations only, and ignored by single-processor configurations.

Integer

0 - Disable. Set for two independent processors.

1 - Lock Step. Appears to the system as two processors but is internally modeled as a single processor.

3 - Split Lock. Appears to the system as two processors but can be statically configured from reset either as two independent processors or two locked processors. For the model, these are equivalent to Disable and Lock Step, respectively, except for the value of build options registers. The model does not support dynamically splitting and locking the processor.

0

MICRO_SCU

Controls whether the effects of the MicroSCU are modeled. You can find more information in the Cortex-R5 Technical Reference Manual. See the reference information at the end of this topic.

Boolean

true/false

true

NUM_BREAKPOINTS

Controls with how many breakpoint pairs the model has been configured. This only affects the build options registers, because debug is not modeled.

Integer

2-8

3

NUM_WATCHPOINTS

Controls with how many watchpoint pairs the model has been configured. This only affects the build options registers, because debug is not modeled.

Integer

1-8

2

dcache-state_modelled

Set whether D-cache has stateful implementation.

Boolean

true/false

false

icache-state_modelled

Set whether I-cache has stateful implementation.

Boolean

true/false

false


The table below provides a description of the configuration parameters for each RTSM_VE_Cortex-R5_MPx1 component processor. These parameters are set individually for each processor you have in your system.

Table 22. RTSM_VE_CortexR5_MPxn coretile parameters - individual cores

Parameter

Description

Type

Allowed Value

Default Value

CFGATCMSZ

Sets the size of the ATCM.

Integer

0x00000000 - 0xE

0xE

CFGBTCMSZ

Sets the size of the BTCM.

Integer

0x00000000 - 0xE

0xE

CFGEND

Initialize to BE8 endianness.

Boolean

true/false

false

CFGIE

Set the reset value of the instruction endian bit.

Boolean

true/false

false

CFGNMFI

Enable nonmaskable FIQ interrupts on startup.

Boolean

true/false

false

DP_FLOAT

Sets whether double-precision instructions are available. You can find more information in the ARM Architecture Reference Manuals. See the reference information at the end of this topic.

Boolean

true/false.

If True, then double precision VFP is supported.

If False, then the VFP is single precision only.

true

NUM_MPU_REGION

Sets the number of MPU regions.

Integer

0x00, 0xC, 0x10.

0 = no MPU.

0xC

TEINIT

Thumb exception enable. The default has exceptions including reset handled in ARM state.

Boolean

true/false

false

VINITHI

Initialize with high vectors enabled.

Boolean

true/false

false

atcm_base[a]

Model-specific. Sets the base address of the ATCM. You can find more information on the processor configuration signals in the Cortex-R5 Technical Reference Manual. See the reference information at the end of this topic.

Integer

0x00000000 - 0xFFFFFFFF

0x40000000

btcm_base[a]

Model-specific. Sets the base address of the BTCM. You can find more information on the processor configuration signals in the Cortex-R5 Technical Reference Manual. See the reference information at the end of this topic.

Integer

0x00000000 - 0xFFFFFFFF

0x00000000

dcache-size

Set D-cache size in bytes.

Integer

0x4000 - 0x10000

0x10000

icache-size

Set I-cache size in bytes.

Integer

0x4000 - 0x10000

0x10000

semihosting-ARM_SVC

ARM SVC number for semihosting.

Integer

0x000000 - 0xFFFFFF

0x123456

semihosting-cmd_line

Command line available to semihosting SVC calls.

String

No limit except memory

[Empty string]

semihosting-enable

Enable semihosting SVC traps.

Caution

Applications that do not use semihosting must set this parameter to False.

Boolean

true/false

true

semihosting-heap_base

Virtual address of heap base.

Integer

0x00000000 - 0xFFFFFFFF

0x0

semihosting-heap_limit

Virtual address of top of heap.

Integer

0x00000000 - 0xFFFFFFFF

0x0F000000

semihosting-stack_base

Virtual address of base of descending stack.

Integer

0x00000000 - 0xFFFFFFFF

0x10000000

semihosting-stack_limit

Virtual address of stack limit.

Integer

0x00000000 - 0xFFFFFFFF

0x0F000000

semihosting-Thumb_SVC

Thumb SVC number for semihosting.

Integer

0x00 - 0xFF

0xAB

vfp-enable_at_reset[a]

Enable coprocessor access and VFP at reset.

Boolean

true/false

false

vfp-present

Set whether model has VFP support.

Boolean

true/false

true

[a] This is a model-specific behavior with no hardware equivalent.


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