RTSM_VE_Cortex-A9 coretile parameters

The table below lists the Cortex-A9 MPCore parameters that you can change when you start the RTSM_VE_Cortex-A9 model. This coretile RTSM is based on r3p0 of the Cortex-A9 MPCore processor.

The table provides a description of the configuration parameters for each Cortex-A9MP core. These parameters are set individually for each Cortex-A9 core you have in your system. Each core has its own timer and watchdog.

The syntax to use in a configuration file is:


where n is the CPU number, from 0 to 3 inclusive.

Table 20. RTSM_VE_Cortex-A9_MPxn coretile parameters for the individual cores

ParameterDescriptionTypeAllowed ValueDefault Value
semihosting-cmd_lineCommand line available to semihosting SVC calls.Stringno limit except memory[empty string]
semihosting-enableEnable semihosting SVC traps.Booleantrue or falsetrue
semihosting-ARM_SVCARM SVC number for semihosting.Integer0x000000 - 0xFFFFFF0x123456
semihosting-Thumb_SVCThumb SVC number for semihosting.Integer0x00 - 0xFF0xAB
semihosting-heap_baseVirtual address of heap base.Integer0x00000000 - 0xFFFFFFFF0x0
semihosting-heap_limitVirtual address of top of heap.Integer0x00000000 - 0xFFFFFFFF0x0F000000
semihosting-stack_baseVirtual address of base of descending stack.Integer0x00000000 - 0xFFFFFFFF0x10000000
semihosting-stack_limitVirtual address of stack limit.Integer0x00000000 - 0xFFFFFFFF0x0F000000

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