Memory configuration

This topic describes memory configuration parameters. See the following table:

Table 25. Memory configuration parameters

ParameterDescriptionDefault
vmsa.implements_fcseSupport fcse in this processorfalse
vmsa.infinite_write_bufferEnable infinite write-buffer.false
vmsa.write_buffer_delayElapsed time between natural buffer drains.1000
vmsa.delayed_read_bufferEnable deferred read values in conjunction with use_IR.false
vmsa.cache_incoherence_checkEnable the check for cache incoherence.false
vmsa.memory_marking_checkEnable the check for inconsistent memory marking in the TLB.false
vmsa.instruction_tlb_lockable_entriesNumber of lockable entries in instruction TLB32
vmsa.instruction_tlb_sizeTotal number of entries in instruction TLB32
vmsa.main_tlb_lockable_entriesNumber of lockable entries in data or unified TLB32
vmsa.main_tlb_sizeTotal number of entries in data or unified TLB32
vmsa.separate_tlbsSeparate ITLB and DTLB. If the TLB is unified, its size is defined by parameter vmsa.main_tlb_size.true
vmsa.tlb_prefetchEnables aggressive pre-fetching into the TLB.false
vmsa.implements_outer_shareableDistinguish between inner shareable and outer shareable memory access types. Outer shareable is implemented as Non Cacheable.true
vmsa.access_flags_hardware_managementEnable support for the hardware management of the Access Flag in the pagetables.true
dcache-state_modelledAllow line allocation in d-side caches at all levelstrue
icache-state_modelledAllow line allocation in i-side caches at all levels. Unified caches allocate lines only if these parameters are enabled at both i-side and d-side.true

The [d|i]cache-state_modelled parameters control the way that caches are simulated. When switched on, the default mode, all cache behaviors and maintenance operations are modeled fully.

If false, the cache is still present in the programmer’s view of the processor but in the simulated implementation there are no memory lines associated with the cache at this level. The programmer-view effect of this is as though the cache cleans and invalidates any line as soon as it is loaded, and can never become incoherent with its backing memory. Although this is an architecturally legal behavior, it is not realistic to any current hardware and is less likely to expose problems in target software. It can, however, be useful when debugging problems that are suspected to be related to cache maintenance, and also has the side effect of permitting the model to run faster.

Compare this to the effect of setting cpu[n].l2dcache-size_bytes = 0, which is to simulate a CPU that contains only Level 1 caches. In this case, the ID code registers do not describe a Level 2 cache. Level 2 is entirely absent from the processor.

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