Real-Time System Model Reference

Version 1.3


List of Topics

Conventions and feedback
Introduction
About system models
About the VE RTSM
About the MPS RTSM
MPS hardware
MPS RTSM
Getting Started with Real-Time System Models
Debugging a RTSM
Starting the RTSM using Model Shell
Configuring VE and MPS RTSMs
Loading and running an application on the VE RTSM
Using the VE CLCD window
Using the MPS Visualisation window
Using Ethernet with a VE RTSM
Using a terminal with a system model
Virtual filesystem
Using the VFS with a pre-built RTSM
Programmer’s Reference for the VE RTSMs
VE model memory map
VE model configuration parameters
Motherboard peripheral parameters
Color LCD controller parameters
Ethernet parameters
System controller parameters
VE system register block parameters
UART parameters
Watchdog parameters
Motherboard virtual component parameters
FLASH loader parameters
Host bridge parameters
MultiMedia Card parameters
Terminal parameters
VFS2 parameters
Visualisation parameters
RTSM_VE_Cortex-A15MPx1, RTSM_VE_Cortex-A15MPx2 and RTSM_VE_Cortex-A15MPx4 coretile parameters
RTSM_VE_Cortex-A9 coretile parameters
RTSM_VE_Cortex-R5_MPx1 and RTSM_VE_Cortex-R5_MPx2 coretile parameters
ARMv7A-AEM
Multicore configuration
General processor configuration
Memory configuration
Cache geometry configuration
Debug architecture configuration
Core configuration
Semihosting configuration
Message configuration
Boundary features and architectural checkers
IMPLEMENTATION DEFINED features
Differences between the VE and coretile hardware and the models
Memory map
Memory aliasing
Features not present in the model
Features partially implemented in the model
Restrictions on the processor models
Timing considerations
Programmer’s Reference for the MPS RTSMs
MPS model memory map
MPS registers
CPU system registers
DUT system registers
Character LCD registers
Memory configuration and remap
Switches
Seven-segment display
MPS configuration parameters
MPS visualisation configuration parameters
DUT configuration parameters
Terminal parameters
Core configuration parameters
Differences between the MPS hardware and the system model
Features not present in the model
Timing considerations

List of Tables

1. Core run state icon descriptions
2. Memory map
3. CS2 peripheral memory map for secure_memory option
4. CS2 peripheral memory map
5. CS3 peripheral memory map
6. Color LCD controller configuration parameters
7. Ethernet configuration parameters
8. System controller configuration parameters
9. System register configuration parameters
10. UART configuration parameters
11. Watchdog configuration parameters
12. FLASH loader configuration parameters
13. Host bridge configuration parameters
14. Multimedia card configuration parameters
15. Terminal configuration parameters
16. VFS2 configuration parameters
17. Visualisation configuration parameters
18. RTSM_VE_Cortex-A15MPxn coretile parameters
19. RTSM_VE_Cortex-A15MPxn coretile parameters - individual cores
20. RTSM_VE_Cortex-A9_MPxn coretile parameters for the individual cores
21. RTSM_VE_CortexR5_MPxn coretile parameters
22. RTSM_VE_CortexR5_MPxn coretile parameters - individual cores
23. Multiprocessing parameters
24. Processor configuration parameters
25. Memory configuration parameters
26. General cache configuration parameters
27. Cache block configuration parameters
28. Debug architecture configuration parameters
29. Core configuration parameters
30. Core configuration parameters
31. Message severity levels
32. Message configuration parameters
33. Overview of MPS memory map
34. MPS CPU system registers
35. MPS DUT system registers
36. MPS LCD registers
37. Memory configuration
38. User switches
39. Seven-segment register
40. Visualisation parameters
41. DUT configuration parameters
42. Terminal instantiation parameters
43. Configuration parameters

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AMay 2011First release for Fast Models 6.1.
Revision BJuly 2011Update for Fast Models v6.2.
Revision CNovember 2011Update for Fast Models v7.0.
Revision DMay 2012Updatefor Fast Models v7.1.
Copyright © 2011-2012 ARM. All rights reserved.ARM DUI 0575D
Non-ConfidentialID051712