Using the VE CLCD window

When a FVP starts, the FVP CLCD window opens, representing the contents of the simulated color LCD frame buffer. It automatically resizes to match the horizontal and vertical resolution set in the CLCD peripheral registers.

The following figure shows the VE FVP CLCD in its default state, immediately after being started.

Figure 3. CLCD window at startup

CLCD window at startup

The top section of the CLCD window displays the following status information:


Eight white boxes show the state of the VE User DIP switches:

These represent switch S6 on the VE hardware, USERSW[8:1], which is mapped to bits [7:0] of the SYS_SW register at address 0x10000004.

The switches are in the off position by default. Click in the area above or below a white box to change its state.


Eight white boxes show the state of the VE Boot DIP switches.

These represent switch S8 on the VE hardware, BOOTSEL[8:1], which is mapped to bits [15:8] of the SYS_SW register at address 0x100000004.

The switches are in the off position by default.


ARM recommends that you configure the Boot DIP switches using the boot_switch model parameter instead of using the CLCD interface. Changing Boot DIP switch positions while the model is running can result in unpredictable behavior.


Eight colored boxes indicate the state of the VE User LEDs.

These represent LEDs D[21:14] on the VE hardware, which are mapped to bits [7:0] of the SYS_LED register at address 0x10000008. The boxes correspond to the red/yellow/green LEDs on the VE hardware.

Total Instr

A counter showing the total number of instructions executed.

Because the FVP models provide a programmer’s view of the system, the CLCD displays total instructions rather than total processor cycles. Timing might differ substantially from the hardware because:

  • the bus fabric is simplified

  • memory latencies are minimized

  • cycle approximate processor and peripheral models are used.

In general bus transaction timing is consistent with the hardware, but timing of operations within the model is not accurate.

Total Time

A counter showing the total elapsed time, in seconds.

This is wall clock time, not simulated time.

Rate Limit

A feature that disables or enables fast simulation.

Because the system model is highly optimized, your code might run faster than it would on real hardware. This might cause timing issues.

Rate Limit is enabled by default. Simulation time is restricted so that it more closely matches real time.

Click on the square button to disable or enable Rate Limit. The text changes from ON to OFF and the colored box becomes darker when Rate Limit is disabled. The figure below shows the CLCD with Rate Limit disabled.


You can control whether Rate Limit is enabled by using the rate_limit-enable parameter, one of the visualization parameters for the MPS Visualization component, when instantiating the model.

When you click on the Total Instr or Total Time items in the CLCD, the display changes to show Inst/sec (instructions per second) and Perf Index (performance index). This is shown in the following figure:

Figure 4. CLCD window with Rate Limit ON

CLCD window with Rate Limit ON

You can click on the items again to toggle between the original and alternative displays.


Shows the number of instructions executed per second of wall clock time.

Perf Index

The ratio of real time to simulation time. The larger the ratio, the faster the simulation runs. If you enable the Rate Limit feature, the Perf Index approaches unity.

You can reset the simulation counters by resetting the model.

The VE FVP CLCD displays the processor run state for each processor in the system by using one of eight colored icons. The icons are located to the left of the Total Instr (or Inst/sec) item, as shown for example in Figure 5:

Figure 5. Processor run state icons for a quad processor model

Processor run state icons for a quad processor model

The description of each of the possible icons is shown in Table 1:

Table 1. Processor run state icon descriptions

IconState labelDescription
UNKNOWNRun status unknown, that is, simulation has not started.
RUNNINGProcessor running, is not idle, and is executing instructions.
HALTEDExternal halt signal asserted.
STANDBY_WFELast instruction executed was WFE and standby mode has been entered.
STANDBY_WFILast instruction executed was WFI and standby mode has been entered.
IN_RESETExternal reset signal asserted.
DORMANTPartial processor power down.
SHUTDOWNComplete processor power down.


The icons do not appear until you start the simulation.

If the CLCD window has focus:


The simulator only sends relative mouse motion events to the model. As a result, the host mouse pointer does not necessarily align with the target OS mouse pointer.

You can hide the host mouse pointer by pressing the Left Ctrl+Left Alt keys. Press the keys again to redisplay the host mouse pointer. Only the Left Ctrl key is operational. The Right Ctrl key on the right of the keyboard does not have the same effect.

If you prefer to use a different key, use the trap_key configuration option, one of the visualization parameters for the MPS Visualization component.

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