ARMv8-A AEM general multiprocessor parameters

You can configure the overall behavior of the models with the general multiprocessor parameters.

Table 32. General multiprocessor parameters[1]

ParameterDescriptionTypeRangeDefault
NUM_CORESNumber of processors implemented.int0x1-0x40x1
is_uniprocessortrue for a uniprocessor implementation. When true, NUM_CORES must be 0x1.boolfalse-truefalse
PA_SIZEPhysical address size, in bits.int0x0-0x300x28
has_16bit_asidsEnable 16-bit Address Space IDentifiers (ASIDs).boolfalse-truetrue
auxilliary_feature_register0Value for Auxiliary Feature Register 0 (ID_AFR0).int

0x0-0xFFFFFFFF

0x0
MIDRValue for Main ID Register (MIDR).int

0x0-0xFFFFFFFF

0x410FD0F0
clear_reg_top_eretClear top 32 bits of general purpose registers on exception return. 0x0 = preserve, 0x1 = clear to zero, 0x2 = random choice of preserve or clear to zero.int0x0-0x20x1
mixed_endianEnable processor to change endianness at runtime. 0x0 = not supported, 0x1 = supported at all exception levels, 0x2 = supported at EL0 only.int0x0-0x20x1
take_ccfail_undefIn AArch32, take Undefined Instruction exception even if the instruction fails its condition-codes check.boolfalse-truetrue
has_thumb2eeEnable T32EE support.[a]boolfalse-truefalse
t32ee_bx_to_armBehavior when T32EE attempts to Branch and Exchange (BX) to A32. 0x0 = stay in T32 state, 0x1 = change to A32 state, 0x2 = handle as Illegal Exception return.int0x0-0x20x0
has_el2Enable EL2.boolfalse-truetrue
has_el3Enable EL3.boolfalse-truetrue
max_32bit_elMaximum exception level supporting AArch32 modes. -0x1 means no support.int-0x1-0x30x3
el0_el1_only_non_secureControls security state of EL0 and EL1 if neither EL2 nor EL3 are implemented. true means non-secure.boolfalse-truefalse
has_writebufferImplement write access buffering before L1 cache. May affect ext_abort behavior.boolfalse-truefalse
has_delayed_sysregDelay the functional effect of system register writes until ISB or implicit barrier.boolfalse-truefalse
tidcp_traps_el0_undef_imp_defThe TIDCP bit traps, in EL0, undefined implementation defined instructions accessing coprocessor registers.boolfalse-truetrue
unpredictable_hvc_behaviourDefine HVC unpredictable behavior in HYP mode, EL2, when the SCR.HCE bit is clear. 0x0 = Undefined Instruction, 0x1 = NOP instruction.int0x0-0x10x0
unpredictable_smc_behaviourDefine SMC unpredictable behavior in Secure mode, EL3, when the SCR.SCD bit is clear. 0x0 = Undefined Instruction, 0x1 = NOP instruction.int0x0-0x10x0
register_reset_dataFill data for register bits when they become unknown at reset.int-0x0
scramble_unknowns_at_resetFill in unknown bits in registers at reset with register_reset_data.boolfalse-truetrue
apsr_read_restrictAt EL0, unknown bits of APSR are RAZ.boolfalse-truefalse
warn_unpredictable_in_v7Warn of unpredictable behavior in ARMv7.boolfalse-truefalse
exercise_stxr_failWhen true, return a pseudorandom majority of Store Exclusive Register (STXR) instructions as Failed.boolfalse-truefalse
delay_serrorMinimum propagation delay of the System Error (SERR) signal into the multiprocessor.[b]int

0x0-0xFFFFFFFF

0x0
has_eagle_cp15_registersIn AArch32 state, enable Cortex™-A15 processor set of implementation defined registers in CP15.boolfalse-truetrue

[1] Terms such as cluster may replace cpu on some systems. The parameter PERIPHBASE is locked down in the VE FVP.

[a] ARM deprecates this optional feature.

[b] Accurate in low-latency mode (-C cpu.scheduler_mode=1), but otherwise any delay might be larger.


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