ARMv8-A AEM debug architecture parameters

You can configure the debug architecture with the debug architecture parameters.

Table 41. Debug architecture parameters

ParameterDescriptionTypeRangeDefault
DBGPIDRIf zero, build a value for the DeBuG Peripheral Identification Register (DBGPIDR). If nonzero, override DBGPIDR with this value.int

0x0-

0xFFFFFFFFFF

0x0
cpu[n].number-of-breakpointsNumber of breakpoints.int0x2-0x100x10
cpu[n].number-of-watchpointsNumber of watchpoints.int0x2-0x100x10
cpu[n].number-of-context-breakpointsNumber of context-aware breakpoints.int0x0-0x100x10
cpu[n].unpredictable_WPMASKANDBASConstrained unpredictable handling of watchpoints when mask and BAS fields specified. 0 = IGNOREMASK, 1 = IGNOREBAS, 2 = REPEATBAS8, 3 = REPEATBAS.int0x0-0x30x1
cpu[n].unpredictable_non-contigous_BASTreat noncontiguous BAS field in watchpoint control register as all ones.boolfalse-truetrue
cpu[n].cti-number_of_triggersNumber of CTI event triggers.int0x0-0x80x8
cpu[n].cti-intack_maskSet bits mean the corresponding triggers need software acknowledgment through CTIINTACK.[a]int0x0-0xFF0x1
v8ect.has_CTIAUTHSTATUSEnable CTIAUTHSTATUS register.boolfalse-truetrue
v8ect.number-of-channelsNumber of channels in Cross Trigger Matrix.int0x3-0x200x4
watchpoint-log2secondary_restrictionLog2(secondary restriction of FAR/EDWAR) on watchpoint hit for load/store operations.int0x0-0x3F0x0

[a] One bit per trigger.


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