ARMv8-A AEM L2 cache-controller parameters

You can configure the Level 2 (L2) cache-controller of the multiprocessor with the L2 cache-controller parameters.

Table 38. L2 cache-controller parameters

ParameterDescriptionTypeRangeDefault
l2cc.cache-state_modelledModel a functional cache stateboolfalse-truefalse
l2cc.ASSOCIATIVITYAssociativity for Auxiliary Control Registerint0x0-0x10x0
l2cc.CACHEIDCache controller cache IDint0x0-0x3F0x0
l2cc.WAYSIZESize of ways for Auxiliary Control Registerint0x0-0x70x1
l2cc.CFGBIGENDAccess configuration registers as big-endian on resetint0x0-0x10x0
l2cc.LOCKDOWN_BY_MASTERLockdown by master[a]int0x0-0x10x0
l2cc.LOCKDOWN_BY_LINELockdown by line[b]int0x0-0x10x0

[a] The value is reflected in CacheType register Bit 26, but the feature is not switched off when the parameter is 0.

[b] The value is reflected in CacheType register Bit 25, but the feature is not switched off when the parameter is 0.


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