ARMv8-A AEM general cache parameters

You can configure the caches of the multiprocessor with the general cache parameters.

Table 37. General cache parameters

cache_maintenance_hits_watchpointsEnable AArch32 cache maintenance by DCIMVAC to trigger watchpoints.[a]boolfalse-truefalse
dcache-state_modelledStateful implementation, with line allocation in D-caches at all levels.[b]boolfalse-truetrue
icache-state_modelledStateful implementation, with line allocation in I-caches at all levels.[b]boolfalse-truetrue
memory.l2_cache.is_inner_cacheableL2 cache is inner cacheable, not outer cacheable.boolfalse-truetrue
memory.l2_cache.is_inner_shareableL2 cache is inner shareable, not outer shareable.boolfalse-truetrue
cache-log2linelenLog2(cache-line length, in bytes)int0x4-0x80x6
cpu[n].DCZID-log2-block-sizeLog2(block size) cleared by DC ZVA instruction[c]int0x0-0x90x8
dcache-sizeL1 D-cache size, in bytesint0x4000-0x1000000x8000
dcache-waysNumber of L1 D-cache ways[d]int0x1-0x400x2
icache-sizeL1 I-cache size, in bytesint0x4000-0x1000000x8000
icache-waysNumber of L1 I-cache ways[d]int0x1-0x400x2
l2cache-sizeL2 cache size, in bytesint0x0-0x10000000x80000
l2cache-waysNumber of L2 cache ways[d]int0x1-0x400x10

[a] unpredictable.

[b] Unified caches allocate lines only if these parameters are enabled at both I-side and D-side.

[c] As read from DCZID_EL0.

[d] Sets are implicit from size.

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