ARMv8-A AEM TLB parameters

You can configure the Translation Lookaside Buffer (TLB) configuration of the multiprocessor with the TLB parameters.

Table 39. TLB parameters

stage12_tlb_sizeNumber of stage 1 and stage 2 TLB entriesint0x1-0xFFFFFFFF0x80
stage1_tlb_sizeNumber of stage 1 TLB entriesint0x0-0xFFFFFFFF0x0
stage2_tlb_sizeNumber of stage 2 TLB entriesint0x0-0xFFFFFFFF0x0
stage1_walkcache_sizeNumber of stage 1 TLB walk cache entriesint0x0-0xFFFFFFFF0x0
stage2_walkcache_sizeNumber of stage 2 TLB walk cache entriesint0x0-0xFFFFFFFF0x0
instruction_tlb_sizeNumber of stage 1 and stage 2 ITLB entries[a]int0x0-0xFFFFFFFF0x0
enable_tlb_contig_checkCheck consistency of TLB entries in regions with the Contiguous Bit setboolfalse-truetrue
has_tlb_conflict_abortInconsistent TLB content generates abortsboolfalse-truefalse
use_tlb_contig_hintPagetable entries with the Contiguous Bit set generate large TLB entriesboolfalse-truefalse

[a] 0 for unified ITLB + DTLB.

Show/hideSee also

Copyright © 2011-2013 ARM. All rights reserved.ARM DUI 0575F