ARMv8-A AEM GIC parameters

You can configure the Generic Interrupt Controller (GIC) behavior of the models with the GIC parameters.

Table 34. GIC parameters

ParameterDescriptionTypeRangeDefault
dic-spi_countNumber of Shared Peripheral Interrupts (SPIs) supported.int0x0-0xE00x40
non_secure_vgic_alias_when_ns_onlyIf no EL3 and no Secure state, the VGIC has a Secure alias. If this parameter is nonzero, the model forms a Non-secure alias from its value for the VGIC, aligned to 32KiB.int

0x0-

0xFFFFFFFFFFFF

0x0
internal_vgicEnable VGIC peripheral.[a]boolfalse-truetrue
gicv3_cpu_interfaceEnable GICv3 processor interface in each processor model.[b]boolfalse-truefalse
gicv3.STATUSR-implementedIf GICv3 processor interface enabled, enable STATUS registers.boolfalse-truetrue
gicv3.IIDR_baseBase value for calculating GICC_IIDR value.int

0x0-0xFFFFFFFF

0x43B
gicv3.BPR-minMinimum value for GICC_BPR.[c]int0x0-0x30x2

[a] Enable unless a shared VGIC is present.

[b] Disable unless a GICv3 distributor is present.

[c] Non-secure copy will be this value + 1.


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