ARMv8-A AEM general processor parameters

Each processor in the multiprocessor has its own parameters. The models use the parameters for processors in sequence, from cpu0 onwards. In cases where fewer processors than the maximum number are instantiated, any parameters for uninstantiated processors are ignored.

Table 35. General processor parameters

ParameterDescriptionTypeRangeDefault
cpu[n].CONFIG64Enable AArch64.boolfalse-truetrue
cpu[n].POWERCTLIDefault power control state.int

0x0-0xFFFFFFFF

0x0
cpu[n].SMPnAMPThis processor is in the inner shared domain, and uses its cache coherency protocol.boolfalse-truetrue
cpu[n].CFGENDUse big-endian order. boolfalse-truefalse
cpu[n].CP15SDISABLEDisable access to some CP15 registers.boolfalse-truefalse
cpu[n].ase-presentEnable NEON™.boolfalse-truetrue
cpu[n].VINITHIEnable high vectors. Base address 0xFFFF0000.boolfalse-truefalse
cpu[n].RVBARReset Vector Base Address when resetting into AArch64.int

0x0-

0xFFFFFFFFFFFC

0x0
cpu[n].vfp-presentEnable floating-point arithmetic.boolfalse-truetrue
cpu[n].vfp-enable_at_resetEnable coprocessor access and VFP at reset.[a]boolfalse-truefalse
cpu[n].vfp-trapsEnable hardware trapping of VFP exceptions for VFPv4U.boolfalse-truetrue
cpu[n].force-fpsidOverride the FPSID value.boolfalse-truefalse
cpu[n].force-fpsid-valueValue for the overridden FPSID.int

0x0-0xFFFFFFFF

0x0
cpu[n].TEINITControls the initial state of SCTLR.TE in AArch32. When set, causes AArch32 exceptions (including reset) to be taken in T32 mode.boolfalse-truefalse
cpu[n].etm-presentEnable Embedded Trace Macrocell (ETM).boolfalse-truetrue
cpu[n].min_sync_levelMinimum CADI syncLevel. 0 = off, 1 = syncState, 2 = postInsnIO, 3 = postInsnAll.int0x0-0x30x0

[a] This is a model-specific behavior with no hardware equivalent.


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