ARMv7-A AEM cache geometry parameters

You can configure the multiprocessor with up to four levels of cache. The cache layout is not required to be symmetrical for each processor in the multiprocessor. The cache geometry parameters repeat in groups cpu0-cpu3, corresponding to the view, for each processor, of the memory hierarchy.

Table 27. General cache parameters

ParameterDescriptionDefault
cpu[n].cache-coherency_level1-based Level of cache coherency. A value of 2 means that the L2 caches, and all subsequent levels, are coherent.2
cpu[n].cache-unification_level1-based Level of cache unification. A value of 2 means that the L2 caches, and all subsequent levels, are unified.2
cpu[n].cache-outer_levelLevel at which outer cache attributes start to be used. L1 caches always use inner attributes. A value of 2 means that the L2 caches, and all subsequent levels, use outer attributes.2

Each cache block in the system is configured using the cache block parameters, which repeat for groups cpu0-cpu3, and within each group in caches l1icache, l1dcache-l4icache, l4dcache.

The number and type of cache blocks are active depending on the unification level of each processor. Before the unification level, caches are separate on the instruction and data sides, and both sets of parameters are used. After the unification level, the data and instruction sides are unified, and the single cache block is described using the data side parameters only.

Table 28. Cache block parameters

ParameterDescriptionDefault
cpu[n].[cache]-size_bytesZero if the cache is not present, otherwise the total size in bytes of the cache. Must be divisible by the line length and associativity, and represent a number of cache sets not greater than 32768.32768
cpu[n].[cache]-linelength_bytesLength of each cache line. Must be 32 or 64.32
cpu[n].[cache]-associativityAssociativity of this cache. Must be between 1 and 1024.4
cpu[n].[cache]-read_allocateSupport allocate-on-read in this cache.true
cpu[n].[cache]-write_allocate[a]Support allocate-on-write in this cache.true
cpu[n].[cache]-write_back[a]Support write-back in this cache.true
cpu[n].[cache]-write_through[a]Support write-through in this cache.true
cpu[n].[cache]-treat_invalidate_as_clean[a]Always clean dirty cache lines before invalidating them.false
cpu[n].[cache]-shared_keyIf nonzero, mark this cache as being shared with other processors.0

[a] This parameter is not applicable to instruction-side caches.


The parameters for each processor describe the view for that processor of the memory hierarchy. If more than one processor has access to the same cache unit, for example, a shared Level 2 cache, then:

You can describe nonlegal cache layouts using the shared_key mechanism. Not all bad cases can be easily detected during initialization, so take care to ensure correct cache configuration. The model might behave erratically if the cache layout cannot be rationalized.

The following figures show examples of processor-cache architecture configurations:

Figure 10. Processor-cache architecture configuration - Example 1

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cpu0.cache-unification_level=2
cpu0.l2dcache-size_bytes=32768
cpu0.l2dcache-shared_key=1
cpu1.cache-unification_level=2
cpu1.l2dcache-size_bytes=32768
cpu1.l2dcache-shared_key=1

Figure 11. Processor-cache architecture configuration - Example 2

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cpu0.cache-unification_level=2
cpu0.l2dcache-size_bytes=32768
cpu0.l2dcache-shared_key=1
cpu0.l3dcache-size_bytes=65536
cpu0.l3dcache-shared_key=2
cpu1.cache-unification_level=1
cpu1.l2dcache-size_bytes=32768
cpu1.l2dcache-shared_key=1
cpu1.l3dcache-size_bytes=65536
cpu1.l3dcache-shared_key=2
cpu2.cache-unification_level=2
cpu2.l2dcache-size_bytes=65536
cpu2.l2dcache-shared_key=2

Note

In the view of CPU2, the shared cache block marked L3U$ is at Level 2 in the memory system hierarchy.

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