ARMv7-A AEM processor parameters

These parameters are repeated in groups cpu0-cpu3, one for each processor in the multiprocessor.

Table 25. Processor parameters

cpu[n].CFGEND0Starts the processor in big endian BE8 mode.false
cpu[n].CFGNMFISets the NMFI bit in the System Control Register (SCTLR) that prevents the FIQ interrupt from being masked in APSR.false
cpu[n].CFGTEStarts the processor in T32 mode.false
cpu[n].CP15SDISABLEDisables access to some CP15 registers.false
cpu[n].VINITHIStarts with high vectors enabled, the vector base address is 0xFFFF0000.false
cpu[n].implements_neonSupport NEON in this processor.true
cpu[n].implements_thumbEESupport T32EE in this processor.true
cpu[n].implements_trustzoneSupport TrustZone™ in this processor.true
cpu[n].implements_vfpSupport VFP in this processor.true
cpu[n].fpsID Value for Floating-point System ID Register.0x41033091
cpu[n].implements_vfpd16-d31If VFP is implemented, support 32 double-precision registers. Otherwise 16 are supported. If NEON is implemented, 32 registers are always supported and this parameter is ignored.true
cpu[n].implements_vfp_short_vectorsEnable support for vfp short vector operations, as indicated by MVFR0[27:24].true
cpu[n].implements_fused_macImplement the vfp fused multiply accumulate operations.false
cpu[n].implements_sdiv_udivImplement the integer divide operations.false
cpu[n].vfp-enable_at_resetVFP registers are enabled without a requirement to write the corresponding access enable bits first.false
cpu[n].SMPnAMPPlace this processor inside the inner shared domain, and participate in the coherency protocol that arranges inner cache coherency among other processors in the domain.false
cpu[n].use_IREnable operation reordering in conjunction with delayed_read_buffer.0

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