Fixed Virtual Platforms VE and MPS FVP Reference Guide

Version 1.4

List of Topics

Conventions and feedback
About system models
About the VE FVP
About the MPS FVP
MPS hardware
Getting Started with Fixed Virtual Platforms
Debugging a FVP
Starting the FVP using Model Shell
Configuring VE and MPS FVPs
Loading and running an application on the VE FVP
Using the VE CLCD window
Using the MPS Visualization window
Using Ethernet with a VE FVP
Using a terminal with a system model
Virtual filesystem
Using the VFS with a prebuilt FVP
Programmer’s Reference for the VE FVPs
VE model memory map
VE model parameters
Motherboard peripheral parameters
Color LCD controller parameters
Ethernet parameters
System controller parameters
VE system register block parameters
UART parameters
Watchdog parameters
Motherboard virtual component parameters
FLASH loader parameters
Host bridge parameters
Multimedia card parameters
Terminal parameters
VFS2 parameters
Visualization parameters
FVP_VE_Cortex-A15MPxn CoreTile parameters
FVP_VE_Cortex-A9 CoreTile parameters
FVP_VE_Cortex-R5_MPxn CoreTile parameters
ARMv7-A AEM parameters
ARMv7-A AEM general multiprocessor parameters
ARMv7-A AEM multiprocessor parameters
ARMv7-A AEM processor parameters
ARMv7-A AEM memory parameters
ARMv7-A AEM cache geometry parameters
ARMv7-A AEM debug architecture parameters
ARMv7-A AEM message parameters
ARMv8-A AEM parameters
ARMv8-A AEM general multiprocessor parameters
ARMv8-A AEM abort parameters
ARMv8-A AEM GIC parameters
ARMv8-A AEM general processor parameters
ARMv8-A AEM cryptography parameters
ARMv8-A AEM general cache parameters
ARMv8-A AEM L2 cache-controller parameters
ARMv8-A AEM TLB parameters
ARMv8-A AEM memory parameters
ARMv8-A AEM debug architecture parameters
ARMv8-A AEM message parameters
ARMv8-A AEM simulator parameters
Semihosting parameters
Boundary features and architectural checkers
Differences between the VE and CoreTile hardware and the models
Memory map
Memory aliasing
Features not present in the model
Features partially implemented in the model
Restrictions on the processor models
Timing considerations
Programmer’s Reference for the MPS FVPs
MPS model memory map
MPS registers
Processor system registers
DUT system registers
Character LCD registers
Memory configuration and remap
Seven-segment display
MPS parameters
MPS visualization parameters
DUT parameters
Terminal parameters
Processor parameters
Differences between the MPS hardware and the system model
Features not present in the model
Timing considerations

List of Tables

1. Processor run state icon descriptions
2. Memory map
3. CS2 peripheral memory map for secure_memory option
4. CS2 peripheral memory map
5. CS3 peripheral memory map
6. Color LCD controller parameters
7. Ethernet parameters
8. System controller parameters
9. System register parameters
10. UART parameters
11. Watchdog parameters
12. FLASH loader parameters
13. Host bridge parameters
14. Multimedia card parameters
15. Terminal parameters
16. VFS2 parameters
17. Visualization parameters
18. FVP_VE_Cortex-A15MPxn CoreTile parameters
19. FVP_VE_Cortex-A15MPxn CoreTile parameters - individual processors
20. FVP_VE_Cortex-A9_MPxn CoreTile parameters - individual processors
21. FVP_VE_CortexR5_MPxn CoreTile parameters
22. FVP_VE_CortexR5_MPxn CoreTile parameters - individual processors
23. multiprocessor parameters
24. Multiprocessing parameters
25. Processor parameters
26. Memory parameters
27. General cache parameters
28. Cache block parameters
29. Debug architecture parameters
30. Message severity levels
31. Message parameters
32. General multiprocessor parameters
33. Abort parameters
34. GIC parameters
35. General processor parameters
36. Cryptography parameters
37. General cache parameters
38. L2 cache-controller parameters
39. TLB parameters
40. Memory parameters
41. Debug architecture parameters
42. Message parameters
43. ARMv8-A AEM simulator parameters
44. Semihosting parameters
45. Overview of MPS memory map
46. MPS processor system registers
47. MPS DUT system registers
48. MPS LCD registers
49. Memory configuration
50. User switches
51. Seven-segment register
52. Visualization parameters
53. DUT parameters
54. Terminal instantiation parameters
55. Processor parameters

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AMay 2011First release for Fast Models v6.1.
Revision BJuly 2011Update for Fast Models v6.2.
Revision CNovember 2011Update for Fast Models v7.0.
Revision DMay 2012Update for Fast Models v7.1.
Revision EDecember 2012Update for Fast Models v8.0.
Revision FMay 2013Update for Fast Models v8.1.
Copyright © 2011-2013 ARM. All rights reserved.ARM DUI 0575F