AMBA 4 ACE and ACE-Lite Protocol Checkers User GuideRevision: r0p1
Home > Implementation and Integration > Implementation and integration flow

2.1. Implementation and integration flow

Figure 2.1 shows the design flow for implementing and integrating the protocol checkers SystemVerilog file with a design.

Figure 2.1. Integration flow

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Copyright © 2011-2012 ARM. All rights reserved.ARM DUI 0576B
Non-ConfidentialID042812
PDF file icon  PDF version
Home > Implementation and Integration > Implementation and integration flow