Unprivileged load and Store, byte, halfword, or word.
When these instructions are executed by privileged software, they access memory with the same restrictions as they would have if they were executed by unprivileged software.
When executed by unprivileged software these instructions
behave in exactly the same way as the corresponding load or store
instruction, for example LDRSBT behaves in the same
way as LDRSB.
Syntaxop{type}T{cond}Rt, [Rn{, #offset}] ; immediate offset (Thumb-2 only)
op{type}T{cond}Rt, [Rn] {, #offset} ; post-indexed (ARM only)
op{type}T{cond}Rt, [Rn], +/-Rm{,shift} ; post-indexed (register) (ARM only)
where:
opcan be either:
LDRLoad Register
STRStore Register.
typecan be any one of:
Bunsigned Byte (Zero extend to 32 bits on loads.)
SBsigned Byte (
LDRonly. Sign extend to 32 bits.)Hunsigned Halfword (Zero extend to 32 bits on loads.)
SHsigned Halfword (
LDRonly. Sign extend to 32 bits.)-omitted, for Word.
condis an optional condition code.
Rtis the register to load or store.
Rnis the register on which the memory address is based.
offsetis an offset. If offset is omitted, the address is the value in
RnRmis a register containing a value to be used as the offset.
Rmshiftis an optional shift.
Table 5 shows the ranges of offsets and availability of these instructions.
Table 7. Offsets and architectures, LDR/STR (User mode)
| Instruction | Immediate offset | Post-indexed | +/-Rm [a] | shift | Arch. |
|---|---|---|---|---|---|
| ARM, word or byte | Not available | -4095 to 4095 | +/- | LSL #0-31 | All |
LSR #1-32 | |||||
ASR #1-32 | |||||
ROR #1-31 | |||||
RRX | |||||
| ARM, signed byte, halfword, or signed halfword | Not available | -255 to 255 | +/- | Not available | v6T2, v7 |
| 32-bit Thumb, word, halfword, signed halfword, byte, or signed byte | 0 to 255 | Not available | Not available | v6T2, v7 | |
[a] You can use -Rm, +Rm, or Rm. | |||||
- Reference:
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