ARM Compiler toolchain v4.1 for µVision Assembler Reference: LDR and STR (immediate offset)

LDR and STR (immediate offset)

Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.

Syntax

op{type}{cond} Rt, [Rn {, #offset}]        ; immediate offset

op{type}{cond} Rt, [Rn, #offset]!          ; pre-indexed

op{type}{cond} Rt, [Rn], #offset           ; post-indexed

opD{cond} Rt, Rt2, [Rn {, #offset}]        ; immediate offset, doubleword

opD{cond} Rt, Rt2, [Rn, #offset]!          ; pre-indexed, doubleword

opD{cond} Rt, Rt2, [Rn], #offset           ; post-indexed, doubleword

where:

op

can be either:

LDR: Load Register
STR: Store Register.

type

can be any one of:

B: unsigned Byte (Zero extend to 32 bits on loads.)
SB: signed Byte (LDR only. Sign extend to 32 bits.)
H: unsigned Halfword (Zero extend to 32 bits on loads.)
SH: signed Halfword (LDR only. Sign extend to 32 bits.)
-: omitted, for Word.

cond

is an optional condition code.

Rt

is the register to load or store.

Rn

is the register on which the memory address is based.

offset

is an offset. If offset is omitted, the address is the contents of Rn.

Rt2

is the additional register to load or store for doubleword operations.

Not all options are available in every instruction set and architecture.

Offset ranges and architectures

Table 5 shows the ranges of offsets and availability of these instructions.

Table 5. Offsets and architectures, LDR/STR, word, halfword, and byte

Instruction	Immediate offset	Pre-indexed	Post-indexed	Arch.
ARM, word or byte ^[a]	-4095 to 4095	-4095 to 4095	-4095 to 4095	All
ARM, signed byte, halfword, or signed halfword	-255 to 255	-255 to 255	-255 to 255	All
ARM, doubleword	-255 to 255	-255 to 255	-255 to 255	v5TE +
32-bit Thumb, word, halfword, signed halfword, byte, or signed byte ^[a]	-255 to 4095	-255 to 255	-255 to 255	v6T2, v7
32-bit Thumb, doubleword	-1020 to 1020 ^[c]	-1020 to 1020 ^[c]	-1020 to 1020 ^[c]	v6T2, v7
16-bit Thumb, word ^[b]	0 to 124 ^[c]	Not available	Not available	All T
16-bit Thumb, unsigned halfword ^[b]	0 to 62 ^[d]	Not available	Not available	All T
16-bit Thumb, unsigned byte ^[b]	0 to 31	Not available	Not available	All T
16-bit Thumb, word, `Rn` is SP ^[e]	0 to 1020 ^[c]	Not available	Not available	All T
16-bit ThumbEE, word ^[b]	-28 to 124 ^[c]	Not available	Not available	T-2EE
16-bit ThumbEE, word, `Rn` is `R9` ^[e]	0 to 252 ^[c]	Not available	Not available	T-2EE
16-bit ThumbEE, word, `Rn` is `R10` ^[e]	0 to 124 ^[c]	Not available	Not available	T-2EE
^[a]For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state. ^[b]Rt and Rn must be in the range R0-R7. ^[c]Must be divisible by 4. ^[d]Must be divisible by 2. ^[e]Rt must be in the range R0-R7.

Register restrictions

Rn must be different from Rt in the pre-index and post-index forms.

Doubleword register restrictions

Rn must be different from Rt2 in the pre-index and post-index forms.

For Thumb instructions, you must not specify SP or PC for either Rt or Rt2.

For ARM instructions:

Rt must be an even-numbered register
Rt must not be LR
it is strongly recommended that you do not use R12 for Rt
Rt2 must be R(t + 1).

Use of PC

In ARM instructions:

You can use PC for Rt in LDR word instructions and PC for Rn in LDR instructions.
You can use PC for Rt in STR word instructions and PC for Rn in STR instructions with immediate offset syntax (that is the forms that do not writeback to the Rn). However, these are deprecated in ARMv6T2 and above.

Other uses of PC are not permitted in these ARM instructions.

In Thumb instructions you can use PC for Rt in LDR word instructions and PC for Rn in LDR instructions. Other uses of PC in these Thumb instructions are not permitted.

Use of SP

You can use SP for Rn.

In ARM, you can use SP for Rt in word instructions. You can use SP for Rt in non-word instructions in ARM code but this is deprecated in ARMv6T2 and above.

In Thumb, you can use SP for Rt in word instructions only. All other use of SP for Rt in these instructions are not permitted in Thumb code.

Examples

    LDR     r8,[r10]            ; loads R8 from the address in R10.
    LDRNE   r2,[r5,#960]!       ; (conditionally) loads R2 from a word
                                ; 960 bytes above the address in R5, and
                                ; increments R5 by 960.
    STR     r2,[r9,#consta-struc]   ; consta-struc is an expression evaluating
                                    ; to a constant in the range 0-4095.

Copyright © 2011 ARM. All rights reserved.	ARM DUI 0588A
Non-Confidential	ID061811
PDF version