PLD, PLDW, and PLI

Preload Data and Preload Instruction. The processor can signal the memory system that a data or instruction load from an address is likely in the near future.

Show/hideSyntax

PLtype{cond} [Rn {, #offset}]
PLtype{cond} [Rn, +/-Rm {, shift}]
PLtype{cond} label

where:

type

can be one of:

D

Data address

DW

Data address with intention to write

I

Instruction address.

type cannot be DW if the syntax specifies label.

cond

is an optional condition code.

Note

cond is permitted only in Thumb-2 code, using a preceding IT instruction. This is an unconditional instruction in ARM and you must not use cond.

Rn

is the register on which the memory address is based.

offset

is an immediate offset. If offset is omitted, the address is the value in Rn.

Rm

is a register containing a value to be used as the offset.

shift

is an optional shift.

label

is a PC-relative expression.

Show/hideRange of offset

The offset is applied to the value in Rn before the preload takes place. The result is used as the memory address for the preload. The range of offsets permitted is:

  • -4095 to +4095 for ARM instructions

  • -255 to +4095 for Thumb-2 instructions, when Rn is not PC.

  • -4095 to +4095 for Thumb-2 instructions, when Rn is PC.

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

Show/hideRegister or shifted register offset

In ARM, the value in Rm is added to or subtracted from the value in Rn. In Thumb-2, the value in Rm can only be added to the value in Rn. The result used as the memory address for the preload.

The range of shifts permitted is:

  • LSL #0 to #3 for Thumb-2 instructions

  • Any one of the following for ARM instructions:

    • LSL #0 to #31

    • LSR #1 to #32

    • ASR #1 to #32

    • ROR #1 to #31

    • RRX

Show/hideAddress alignment for preloads

No alignment checking is performed for preload instructions.

Show/hideRegister restrictions

Rm must not be PC. For Thumb instructions Rm must also not be SP.

Rn must not be PC for Thumb instructions of the syntaxPLtype{cond} [Rn, +/-Rm{, #shift}].

Show/hideArchitectures

ARM PLD is available in ARMv5TE and above.

32-bit Thumb PLD is available in ARMv6T2 and above.

PLDW is available only in ARMv7 and above that implement the Multiprocessing Extensions.

PLI is available only in ARMv7 and above.

There are no 16-bit Thumb PLD, PLDW, or PLI instructions.

These are hint instructions, and their implementation is optional. If they are not implemented, they execute as NOPs.

Show/hideSee also

Concepts
Reference:
Copyright © 2011 ARM. All rights reserved.ARM DUI 0588A
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