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Home > VFP Programming > VFP instructions > VFMA, VFMS, VFNMA, VFNMS |

Fused floating-point multiply accumulate and fused floating-point multiply subtract with optional negation.

These instructions are always scalar.

VF{N}`{`

`op`

}.F64 {`cond`

},`Dd`

,`Dn`

`Dm`

VF{N}{`op`

}.F32 {`cond`

},`Sd`

,`Sn`

`Sm`

where:

`op`

is one of

`MA`

or`MS`

.`N`

negates the final result.

`cond`

is an optional condition code.

,`Sd`

,`Sn`

`Sm`

are the single-precision registers for the result and operands.

,`Dd`

,`Dn`

`Dm`

are the double-precision registers for the result and operands.

,`Qd`

,`Qn`

`Qm`

are the double-precision registers for the result and operands.

`VFMA`

multiplies the values in the operand registers,
adds the value in the destination register, and places the final
result in the destination register. The result of the multiply is
not rounded before the accumulation.

`VFMS`

multiplies the values in the operand registers,
subtracts the product from the value in the destination register,
and places the final result in the destination register. The result
of the multiply is not rounded before the subtraction.

In each case, the final result is negated if the `N`

option
is used.

These instructions can produce Input Denormal, Invalid Operation, Overflow, Underflow, or Inexact exceptions.

- Concepts
*Using the Assembler*:- Reference: