ADRL pseudo-instruction

Load a PC-relative or register-relative address into a register. It is similar to the ADR instruction. ADRL can load a wider range of addresses than ADR because it generates two data processing instructions.


ADRL is only available when assembling Thumb instructions ARMv6T2 and later.


ADRL{cond} Rd,label



is an optional condition code.


is the register to load.


is a PC-relative or register-relative expression.


ADRL always assembles to two 32-bit instructions. Even if the address can be reached in a single instruction, a second, redundant instruction is produced.

If the assembler cannot construct the address in two instructions, it generates an error message and the assembly fails. You can use the LDR pseudo-instruction for loading a wider range of addresses.

ADRL produces position-independent code, because the address is PC-relative or register-relative.

If label is PC-relative, it must evaluate to an address in the same assembler area as the ADRL pseudo-instruction.

If you use ADRL to generate a target for a BX or BLX instruction, it is your responsibility to set the Thumb bit (bit 0) of the address if the target contains Thumb instructions.

Show/hideArchitectures and range

The available range depends on the instruction set in use:


±64KB to a byte or halfword-aligned address.

±256KB bytes to a word-aligned address.

32-bit Thumb

±1MB bytes to a byte, halfword, or word-aligned address.

16-bit Thumb

ADRL is not available.

The given range is relative to a point four bytes (in Thumb code) or two words (in ARM code) after the address of the current instruction. More distant addresses can be in range if the alignment is 16-bytes or more relative to this point.

Show/hideSee also

Copyright © 2011 ARM. All rights reserved.ARM DUI 0588A