ARM Compiler toolchain v4.1 for µVision Assembler Reference: SMLAD and SMLSD

SMLAD and SMLSD

Dual 16-bit Signed Multiply with Addition or Subtraction of products and 32-bit accumulation.

Syntax

op{X}{cond} Rd, Rn, Rm, Ra

where:

op

is one of:

SMLAD: Dual multiply, accumulate sum of products.
SMLSD: Dual multiply, accumulate difference of products.

cond

is an optional condition code.

X

is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.

Rd

is the destination register.

Rn, Rm

are the registers holding the operands.

Ra

is the register holding the accumulate operand.

Operation

SMLAD multiplies the bottom halfword of Rn with the bottom halfword of Rm, and the top halfword of Rn with the top halfword of Rm. It then adds both products to the value in Ra and stores the sum to Rd.

SMLSD multiplies the bottom halfword of Rn with the bottom halfword of Rm, and the top halfword of Rn with the top halfword of Rm. It then subtracts the second product from the first, adds the difference to the value in Ra, and stores the result to Rd.

Register restrictions

You cannot use PC for any register.

You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Condition flags

These instructions do not change the flags.

Architectures

These ARM instructions are available in ARMv6 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.

There are no 16-bit Thumb versions of these instructions.

Examples

    SMLSD       r1, r2, r0, r7
    SMLSDX      r11, r10, r2, r3
    SMLADLT     r1, r2, r4, r1

Copyright © 2011 ARM. All rights reserved.	ARM DUI 0588A
Non-Confidential	ID061811
PDF version