### SMMUL, SMMLA, and SMMLS

Signed Most significant word Multiply, Signed Most significant word Multiply with Accumulation, and Signed Most significant word Multiply with Subtraction. These instructions have 32-bit operands and produce only the most significant 32-bits of the result.

#### Syntax

````SMMUL`{R}{`cond`} {`Rd`}, `Rn`, `Rm`
```
````SMMLA`{R}{`cond`} `Rd`, `Rn`, `Rm`, `Ra`
```
````SMMLS`{R}{`cond`} `Rd`, `Rn`, `Rm`, `Ra`
```

where:

`R`

is an optional parameter. If `R` is present, the result is rounded, otherwise it is truncated.

`cond`

is an optional condition code.

`Rd`

is the destination register.

`Rn, Rm`

are the registers holding the operands.

`Ra`

is a register holding the value to be added or subtracted from.

#### Operation

`SMMUL` multiplies the values from `Rn` and `Rm`, and stores the most significant 32 bits of the 64-bit result to `Rd`.

`SMMLA` multiplies the values from `Rn` and `Rm`, adds the value in `Ra` to the most significant 32 bits of the product, and stores the result in `Rd`.

`SMMLS` multiplies the values from `Rn` and `Rm`, subtracts the product from the value in `Ra` shifted left by 32 bits, and stores the most significant 32 bits of the result in `Rd`.

If the optional `R` parameter is specified, `0x80000000` is added before extracting the most significant 32 bits. This has the effect of rounding the result.

#### Register restrictions

You cannot use PC for any register.

You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

#### Condition flags

These instructions do not change the flags.

#### Architectures

These ARM instructions are available in ARMv6 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.

There are no 16-bit Thumb versions of these instructions.

#### Examples

```    SMMULGE     r6, r4, r3
SMMULR      r2, r2, r2
```