### SXT, SXTA, UXT, and UXTA

Sign extend, Sign extend with Add, Zero extend, and Zero extend with Add.

#### Syntax

```SXT<`extend`>{`cond`}  {`Rd`}, `Rm  `{,`rotation`}
```
```SXTA<`extend`>{`cond`} {`Rd`}, `Rn`, `Rm `{,`rotation`}
```
```UXT<`extend`>{`cond`}  {`Rd`}, `Rm`  {,`rotation`}
```
```UXTA<`extend`>{`cond`} {`Rd`}, `Rn`, `Rm` {,`rotation`}
```

where:

`<extend>`

is one of:

`B16`

Extends two 8-bit values to two 16-bit values.

`B`

Extends an 8-bit value to a 32-bit value.

`H`

Extends a 16-bit value to a 32-bit value.

`cond`

is an optional condition code.

`Rd`

is the destination register.

`Rn`

is the register holding the number to add (`SXTA` and `UXTA` only).

`Rm`

is the register holding the value to extend.

`rotation`

is one of:

`ROR #8`

Value from `Rm` is rotated right 8 bits.

`ROR #16`

Value from `Rm` is rotated right 16 bits.

`ROR #24`

Value from `Rm` is rotated right 24 bits.

If `rotation` is omitted, no rotation is performed.

#### Operation

These instructions do the following:

1. Rotate the value from `Rm` right by 0, 8, 16 or 24 bits.

2. Do one of the following to the value obtained:

• Extract bits[7:0], sign or zero extend to 32 bits. If the instruction is extend and add, add the value from `Rn`.

• Extract bits[15:0], sign or zero extend to 32 bits. If the instruction is extend and add, add the value from `Rn`.

• Extract bits[23:16] and bits[7:0] and sign or zero extend them to 16 bits. If the instruction is extend and add, add them to bits[31:16] and bits[15:0] respectively of `Rn` to form bits[31:16] and bits[15:0] of the result.

#### Register restrictions

You cannot use PC for any register.

You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

#### Condition flags

These instructions do not change the flags.

#### 16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions:

`SXTB Rd, Rm`

`Rd` and `Rm` must both be Lo registers.

`SXTH Rd, Rm`

`Rd` and `Rm` must both be Lo registers.

`UXTB Rd, Rm`

`Rd` and `Rm` must both be Lo registers.

`UXTH Rd, Rm`

`Rd` and `Rm` must both be Lo registers.

#### Architectures

These ARM instructions are available in ARMv6 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.

These 16-bit Thumb instructions are available in ARMv6 and above.

#### Examples

```    SXTH         r3, r9, r4
UXTAB16EQ    r0, r0, r4, ROR #16
```

#### Incorrect examples

```    SXTH     r9, r3, r2, ROR #12 ; rotation must be by 0, 8, 16, or 24.
```