ARM® Compiler toolchain v4.1 for µVision Assembler Reference


List of Topics

Conventions and feedback
Assembler command line options
Assembler command line syntax
Assembler command line options
--16
--32
--apcs=qualifier…qualifier
--arm
--arm_only
--bi
--bigend
--brief_diagnostics
--checkreglist
--compatible=name
--cpreproc
--cpreproc_opts=options
--cpu=list
--cpu=name
--debug
--depend=dependfile
--depend_format=string
--diag_error=tag{, tag}
--diag_remark=tag{, tag}
--diag_style=style
--diag_suppress=tag{, tag}
--diag_warning=tag{, tag}
--dllexport_all
--dwarf2
--dwarf3
--errors=errorfile
--execstack
--exceptions
--exceptions_unwind
--fpmode=model
--fpu=list
--fpu=name
-g
--help
-idir{,dir, …}
--keep
--length=n
--li
--library_type=lib
--list=file
--list=
--littleend
-m
--maxcache=n
--md
--no_code_gen
--no_esc
--no_execstack
--no_exceptions
--no_exceptions_unwind
--no_hide_all
--no_project
--no_reduce_paths
--no_regs
--no_terse
--no_unaligned_access
--no_warn
-o filename
--pd
--predefine "directive"
--project=filename
--reduce_paths
--regnames=none
--regnames=callstd
--regnames=all
--reinitialize_workdir
--report-if-not-wysiwyg
--show_cmdline
--split_ldm
--thumb
--thumbx
--unaligned_access
--unsafe
--untyped_local_labels
--version_number
--via=file
--vsn
--width=n
--workdir=directory
--xref
ARM and Thumb Instructions
Instruction summary
Instruction width specifiers
Memory access instructions
LDR and STR (immediate offset)
LDR and STR (register offset)
LDR and STR, unprivileged
LDR (PC-relative)
LDR (register-relative)
ADR (PC-relative)
ADR (register-relative)
PLD, PLDW, and PLI
LDM and STM
PUSH and POP
RFE
SRS
LDREX and STREX
CLREX
SWP and SWPB
General data processing instructions
Flexible second operand (Operand2)
Operand 2 as a constant
Operand2 as a register with optional shift
Shift Operations
ADD, SUB, RSB, ADC, SBC, and RSC
SUBS pc, lr
AND, ORR, EOR, BIC, and ORN
CLZ
CMP and CMN
MOV and MVN
MOVT
TST and TEQ
SEL
REV, REV16, REVSH, and RBIT
ASR, LSL, LSR, ROR, and RRX
SDIV and UDIV
Multiply instructions
MUL, MLA, and MLS
UMULL, UMLAL, SMULL, and SMLAL
SMULxy and SMLAxy
SMULWy and SMLAWy
SMLALxy
SMUAD{X} and SMUSD{X}
SMMUL, SMMLA, and SMMLS
SMLAD and SMLSD
SMLALD and SMLSLD
UMAAL
MIA, MIAPH, and MIAxy
Saturating instructions
Saturating arithmetic
QADD, QSUB, QDADD, and QDSUB
SSAT and USAT
Parallel instructions
Parallel add and subtract
USAD8 and USADA8
SSAT16 and USAT16
Packing and unpacking instructions
BFC and BFI
SBFX and UBFX
SXT, SXTA, UXT, and UXTA
PKHBT and PKHTB
Branch and control instructions
B, BL, BX, BLX, and BXJ
IT
CBZ and CBNZ
TBB and TBH
Coprocessor instructions
CDP and CDP2
MCR, MCR2, MCRR, and MCRR2
MRC, MRC2, MRRC and MRRC2
MSR
MRS
SYS
LDC, LDC2, STC, and STC2
Miscellaneous instructions
BKPT
SVC
MRS
MSR
CPS
SMC
SETEND
NOP
SEV, WFE, WFI, and YIELD
DBG
DMB, DSB, and ISB
MAR and MRA
ThumbEE instructions
ENTERX and LEAVEX
CHKA
HB, HBL, HBLP, and HBP
Pseudo-instructions
ADRL pseudo-instruction
MOV32 pseudo--instruction
LDR pseudo-instruction
UND pseudo-instruction
Condition codes
VFP Programming
VFP instruction summary
VFP pseudo-instructions
VLDR pseudo-instruction
VLDR and VSTR (post-increment and pre-decrement)
VFP instructions
VABS, VNEG, and VSQRT
VADD, VSUB, and VDIV
VLDR and VSTR
VLDM, VSTM, VPOP, and VPUSH
VMOV (between two ARM registers and an extension register)
VMOV (between one ARM register and single precision VFP)
VMRS and VMSR
VMUL, VMLA, VMLS, VNMUL, VNMLA, and VNMLS
VFMA, VFMS, VFNMA, VFNMS
VCMP
VCVT (between single-precision and double-precision)
VCVT (between floating-point and integer)
VCVT (between floating-point and fixed-point)
VCVTB, VCVTT (half-precision extension)
VMOV
Directives Reference
Alphabetical list of directives
Symbol definition directives
GBLA, GBLL, and GBLS
LCLA, LCLL, and LCLS
SETA, SETL, and SETS
RELOC
RN
RLIST
CN
CP
DN and SN
Data definition directives
LTORG
MAP
FIELD
SPACE or FILL
DCB
DCD and DCDU
DCDO
DCFD and DCFDU
DCFS and DCFSU
DCI
DCQ and DCQU
DCW and DCWU
COMMON
DATA
Assembly control directives
Nesting directives
MACRO and MEND
MEXIT
IF, ELSE, ENDIF, and ELIF
WHILE and WEND
Frame directives
FRAME ADDRESS
FRAME POP
FRAME PUSH
FRAME REGISTER
FRAME RESTORE
FRAME RETURN ADDRESS
FRAME SAVE
FRAME STATE REMEMBER
FRAME STATE RESTORE
FRAME UNWIND ON
FRAME UNWIND OFF
FUNCTION or PROC
ENDFUNC or ENDP
Reporting directives
ASSERT
INFO
OPT
TTL and SUBT
Instruction set and syntax selection directives
ARM, THUMB, THUMBX, CODE16 and CODE32
Miscellaneous directives
ALIAS
ALIGN
AREA
ATTR
END
ENTRY
EQU
EXPORT or GLOBAL
EXPORTAS
GET or INCLUDE
IMPORT and EXTERN
INCBIN
KEEP
NOFP
REQUIRE
REQUIRE8 and PRESERVE8
ROUT

List of Figures

1. ASR #3
2. LSR #3
3. LSL #3
4. ROR #3
5. RRX

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AJune 2011Release for ARM Compiler toolchain v4.1 for µVision
Copyright © 2011 ARM. All rights reserved.ARM DUI 0588A
Non-ConfidentialID061811