LDR and STR, unprivileged

Unprivileged load and Store, byte, halfword, or word.

When these instructions are executed by privileged software, they access memory with the same restrictions as they would have if they were executed by unprivileged software.

When executed by unprivileged software these instructions behave in exactly the same way as the corresponding load or store instruction, for example LDRSBT behaves in the same way as LDRSB.

Show/hideSyntax

op{type}T{cond} Rt, [Rn {, #offset}]       ; immediate offset (32-bit Thumb only)
op{type}T{cond} Rt, [Rn] {, #offset}       ; post-indexed (ARM only)
op{type}T{cond} Rt, [Rn], +/-Rm {, shift}  ; post-indexed (register) (ARM only)

where:

op

can be either:

LDR

Load Register

STR

Store Register.

type

can be any one of:

B

unsigned Byte (Zero extend to 32 bits on loads.)

SB

signed Byte (LDR only. Sign extend to 32 bits.)

H

unsigned Halfword (Zero extend to 32 bits on loads.)

SH

signed Halfword (LDR only. Sign extend to 32 bits.)

-

omitted, for Word.

cond

is an optional condition code.

Rt

is the register to load or store.

Rn

is the register on which the memory address is based.

offset

is an offset. If offset is omitted, the address is the value in Rn.

Rm

is a register containing a value to be used as the offset. Rm must not be PC.

shift

is an optional shift.

Show/hideOffset ranges and architectures

Table 11 shows the ranges of offsets and availability of these instructions.

Table 11. Offsets and architectures, LDR/STR (User mode)

InstructionImmediate offsetPost-indexed+/-Rm [a]shiftArch.[b]
ARM, word or byteNot available-4095 to 4095+/-RmLSL #0-31All
    LSR #1-32 
    ASR #1-32 
    ROR #1-31 
    RRX 
ARM, signed byte, halfword, or signed halfwordNot available-255 to 255+/-RmNot availableT2
32-bit Thumb, word, halfword, signed halfword, byte, or signed byte0 to 255Not availableNot availableT2

[a] You can use -Rm, +Rm, or Rm.

[b] Entries in the Architecture column indicate that the instructions are available as follows:

All

All versions of the ARM architecture.

T2

The ARMv6T2 and above architectures.


Show/hideSee also

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