LDR and STR (register offset)

Load and Store with register offset, pre-indexed register offset, or post-indexed register offset.

Show/hideSyntax

op{type}{cond} Rt, [Rn, +/-Rm {, shift}]   ; register offset
op{type}{cond} Rt, [Rn, +/-Rm {, shift}]!  ; pre-indexed       ; ARM only
op{type}{cond} Rt, [Rn], +/-Rm {, shift}   ; post-indexed      ; ARM only
opD{cond} Rt, Rt2, [Rn, +/-Rm]   ; register offset, doubleword ; ARM only
opD{cond} Rt, Rt2, [Rn, +/-Rm]!  ; pre-indexed, doubleword     ; ARM only
opD{cond} Rt, Rt2, [Rn], +/-Rm   ; post-indexed, doubleword    ; ARM only

where:

op

can be either:

LDR

Load Register

STR

Store Register.

type

can be any one of:

B

unsigned Byte (Zero extend to 32 bits on loads.)

SB

signed Byte (LDR only. Sign extend to 32 bits.)

H

unsigned Halfword (Zero extend to 32 bits on loads.)

SH

signed Halfword (LDR only. Sign extend to 32 bits.)

-

omitted, for Word.

cond

is an optional condition code.

Rt

is the register to load or store.

Rn

is the register on which the memory address is based.

Rm

is a register containing a value to be used as the offset. -Rm is not permitted in Thumb code.

shift

is an optional shift.

Rt2

is the additional register to load or store for doubleword operations.

Not all options are available in every instruction set and architecture.

Show/hideOffset register and shift options

Table 10 shows the ranges of offsets and availability of these instructions.

Table 10. Options and architectures, LDR/STR (register offsets)

Instruction+/-Rm [a]shift  Arch.[b]
ARM, word or byte [c]+/-RmLSL #0-31LSR #1-32 All
  ASR #1-32ROR #1-31RRX 
ARM, signed byte, halfword, or signed halfword+/-RmNot availableAll
ARM, doubleword+/-RmNot available5E
32-bit Thumb, word, halfword, signed halfword, byte, or signed byte [c]+RmLSL #0-3  T2
16-bit Thumb, all except doubleword[d]+RmNot availableT
16-bit ThumbEE, word [c]+RmLSL #2 (required)EE
16-bit ThumbEE, halfword, signed halfword [c]+RmLSL #1 (required)EE
16-bit ThumbEE, byte, signed byte [c]+RmNot availableEE

[a] Where +/-Rm is shown, you can use -Rm, +Rm, or Rm. Where +Rm is shown, you cannot use -Rm.

[b] Entries in the Architecture column indicate that the instructions are available as follows:

All

All versions of the ARM architecture.

5E

The ARMv5TE, ARMv6*, and ARMv7 architectures.

T2

The ARMv6T2 and above architectures.

T

The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

EE

ThumbEE variants of the ARM architecture.

[c] For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state.

[d] Rt, Rn, and Rm must all be in the range R0-R7.


Show/hideRegister restrictions

In the pre-index and post-index forms:

  • Rn must be different from Rt

  • Rn must be different from Rm in architectures before ARMv6.

Show/hideDoubleword register restrictions

For ARM instructions:

  • Rt must be an even-numbered register

  • Rt must not be LR

  • it is strongly recommended that you do not use R12 for Rt

  • Rt2 must be R(t + 1)

  • Rm must be different from Rt and Rt2 in LDRD instructions

  • Rn must be different from Rt2 in the pre-index and post-index forms.

Show/hideUse of PC

In ARM instructions:

  • You can use PC for Rt in LDR word instructions, and you can use PC for Rn in LDR instructions with register offset syntax (that is the forms that do not writeback to the Rn).

  • You can use PC for Rt in STR word instructions, and you can use PC for Rn in STR instructions with register offset syntax (that is the forms that do not writeback to the Rn). However, these are deprecated in ARMv6T2 and above.

Other uses of PC are not permitted in ARM instructions.

In Thumb instructions you can use PC for Rt in LDR word instructions. Other uses of PC in these Thumb instructions are not permitted.

Show/hideUse of SP

You can use SP for Rn.

In ARM, you can use SP for Rt in word instructions. You can use SP for Rt in non-word ARM instructions but this is deprecated in ARMv6T2 and above.

You can use SP for Rm in ARM instructions but this is deprecated in ARMv6T2 and above.

In Thumb, you can use SP for Rt in word instructions only. All other use of SP for Rt in these instructions are not permitted in Thumb code.

Use of SP for Rm is not permitted in Thumb state.

Show/hideSee also

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