ADR (register-relative)

ADR generates a register-relative address in the destination register, for a label defined in a storage map.


ADR{cond}{.W} Rd,label



is an optional condition code.


is an optional instruction width specifier.


is the destination register to load.


is a symbol defined by the FIELD directive. label specifies an offset from the base register which is defined using the MAP directive.

label must be within a limited distance from the base register.


ADR generates code to easily access named fields inside a storage map.

Use the ADRL pseudo-instruction to assemble a wider range of effective addresses.


In Thumb code:

  • Rd cannot be PC

  • Rd can be SP only if the base register is SP.

Show/hideOffset range and architectures

The assembler calculates the offset from the base register for you. The assembler generates an error if label is out of range.

Table 7 shows the possible offsets between the label and the current instruction.

Table 7. register-relative offsets

InstructionOffset rangeArchitectures[a]
ARM ADRSee Operand2 as a constantAll
32-bit Thumb ADR+/- 4095T2
16-bit Thumb ADR, base register is SP [b]0-1020 [c]T

[a] Entries in the Architectures column indicate that the instructions are available as follows:


All versions of the ARM architecture.


The ARMv6T2 and above architectures.


The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

[b] Rd must be in the range R0-R7 or SP. If Rd is SP, the offset range is -508 to 508 and must be a multiple of 4

[c] Must be a multiple of 4.

Show/hideADR in 32-bit Thumb

You can use the .W width specifier to force ADR to generate a 32-bit instruction in Thumb code. ADR with .W always generates a 32-bit instruction, even if the address can be generated in a 16-bit instruction.

For forward references, ADR without .W, with base register SP, always generates a 16-bit instruction in Thumb code, even if that results in failure for an address that could be generated in a 32-bit Thumb ADD instruction.

Show/hideSee also

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