SDIV and UDIV

Signed and Unsigned Divide.

Show/hideSyntax

SDIV{cond} {Rd}, Rn, Rm
UDIV{cond} {Rd}, Rn, Rm

where:

cond

is an optional condition code.

Rd

is the destination register.

Rn

is the register holding the value to be divided.

Rm

is a register holding the divisor.

Show/hideRegister restrictions

PC or SP cannot be used for Rd, Rn or Rm.

Show/hideArchitectures

These 32-bit Thumb instructions are available in ARMv7-R and ARMv7-M only.

There are no ARM or 16-bit Thumb SDIV and UDIV instructions.

Show/hideSee also

Reference
Copyright © 2011-2012 ARM. All rights reserved.ARM DUI 0588B
Non-ConfidentialID062912